碳化硅MOSFET的变温度参数建模

为在全温度范围内准确反映碳化硅(silicon carbide,SiC)MOSFET的工作特性,提出一种基于Pspice仿真软件的SiC MOSFET变温度参数模型。该模型中引入温控电压源和温控电流源以补偿SiC MOSFET静态特性随温度的变化,同时着重考虑了SiC MOSFET的低温特性和驱动电路负压的影响。详细阐述建模原理,分析各个关键参数对SiCMOSFET静态特性及动态特性的影响,给出建模原理。搭建基于Buck变换器的SiC MOSFET测试实验样机,在不同电压点、电流点及温度点(25-125℃)下进行实验测试,并将测试结果与基于变温度参数Pspice模型的仿真波形和损耗估算结果进行比较。比较结果高度吻合,功率损耗误差在10%以内,验证了提出的变温度参数模型的准确性和有效性,为实际应用中采用SiC MOSFET器件进行系统分析和效率评估提供了重要的依据。     

考虑变温度影响的SiC MOSFET建模与分析

为了准确反映SiC MOSFET在不同温度下的电气特性,对影响SiC MOSFET电气特性的关键参数进行了分析,提出了一种SiC MOSFET等效电路模型。首先,根据SiC MOSFET阈值电压和跨导随温度变化的规律,采用函数拟合的温控电源模型对SiC MOSFET的阈值电压和漏极电流进行补偿;其次,考虑寄生电容与极间电压的关系,采用电容子电路和可变电容模型对SiC MOSFET的寄生电容进行等效模拟,根据SiC MOSFET体二极管对其静、动态特性的影响,利用独立二极管模型描述体二极管特性,进而建立SiC MOSFET的等效电路模型。最后,在不同温度条件下,对该模型进行了仿真并与实验测试结果进行了对比。结果表明所建模型较为准确地描述SiC MOSFET在较宽温度范围内的静、动态特性,验证了模型的有效性。     

适用于电动汽车的SiC MOSFET PSpice仿真模型研究

为了基于PSpice电路对电动汽车DC/DC变换器中的碳化硅(SiC)MOSFET的工作特性进行实时准确地仿真,针对SiC MOSFET提出了一种新型的电压控制电流源型VCCST(voltage-controlled current source type)PSpice仿真模型。首先,为了获得SiC MOSFET准确的静态特性建立了电压控制电流源作为SiC MOSFET的内核,以描述SiC MOSFET的转移特性和输出特性;然后,为了获得SiC MOSFET准确的动态特性,建立了基于电压控制电流源与恒定电容的栅漏电容(CGD)子电路模型,所提SiC MOSFET VCCST PSpice模型在简化参数提取方法的同时,能够满足模型准确性的要求;最后,建立的SiC MOSFET VCCST PSpice模型应用于Boost变换器进行仿真和实验,并对SiC MOSFET的特性进行测试。测试结果验证了所提SiC MOSFET VCCST PSpice仿真模型的准确性和实时性,从而为SiC MOSFET在电动汽车DC/DC变换器中的设计和应用提供了便利。     

不同雪崩冲击模式下SiC MOSFET的失效机理

在高开关速度di/dt和寄生电感的耦合下,SiC MOSFET器件极易进入雪崩工作模式。针对现有单一实验失效分析难以揭示不同雪崩冲击模式可能引起不同失效模式的问题,提出在单次和重复雪崩冲击下SiC MOSFET器件失效机理的实验与仿真研究。首先,搭建SiC MOSFET非钳位电感(unclamped inductive switching,UIS)雪崩实验平台及元胞级仿真模型。其次,基于单次脉冲雪崩冲击实验建立SiC MOSFET对应失效模型,获取单次脉冲下失效演化中元胞电热分布规律。最后,基于重复雪崩冲击失效实验,建立SiC MOSFET对应失效演化模型,仿真性能退化特征参数,获取重复雪崩冲击下失效演化过程的电场分布规律。实验和仿真表明,单次脉冲雪崩冲击下寄生BJT闩锁造成SiC MOSFET器件失效;而氧化层捕获空穴形成氧化层固定电荷会导致器件后期阈值电压降低,引起重复雪崩冲击下器件失效。     

基于SiC MOSFET户用光伏逆变器的效率分析

户用型光伏逆变器的发展趋势是高频化、高效率、高功率密度,近年来,SiC MOSFET在电机驱动、光伏逆变器等场合得到了广泛研究。本文将SiC MOSFET应用于1.6kW两级式光伏逆变器中,提高逆变器的开关频率,对前后两级独立进行了效率分析。在前级Boost中,比较了20 kHz 到100kHz 开关频率下,SiC MOSFET和Si MOSFET 对Boost效率的影响;在后级逆变器中,比较了100 kHz SiC MOSFET逆变器与20 kHz Si MOSFET H6逆变器的效率。搭建了1.6kW两级式光伏逆变器实验模型,采用SiC MOSFET,并在逆变器实验模型上对分析结果进行了实验验证。     

计及温度影响的SiC MOSFET芯片热网络建模

针对雪崩工况下碳化硅(SiC)金属-氧化物-半导体场效应晶体管(MOSFET)芯片温升大影响材料热参数变化,往往导致温度计算不准确的问题,提出计及材料热参数温度依赖性的芯片瞬态热网络模型.首先,分析SiC MOSFET芯片材料的温度依赖性,采用多项式拟合获取热参数随温度变化规律;其次,利用扫描电子显微镜获取SiC MOSFET芯片几何参数,建立芯片元胞模型并通过实验验证其准确性,获取雪崩过程电压电流波形;最后,考虑温度对材料热参数的影响,建立SiC MOSFET芯片瞬态热网络模型,揭示雪崩工况下芯片温度变化规律.结果表明,与不考虑温度影响模型相比,所建芯片瞬态热网络模型更能准确地反映雪崩全过程芯片温度变化,且芯片温度骤升主要体现在内部,外部影响少.     

SiC MOSFET串联短路动态特性

在电力电子系统中,因器件击穿、硬件电路缺陷或系统控制失误导致碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)误开通时,桥臂电流回路中多个器件处于开通状态,形成串联短路故障.该文以SiC MOSFET半桥电路为研究对象,详细介绍SiC MOSFET串联短路的动态过程,理论分析负载电流、栅极驱动电压和结温温升对SiC MOSFET短路动态特性的影响规律,推导出SiC MOSFET分压模型,并采用仿真模型进行验证.实验基于1200V/80A SiC MOSFET测试平台验证电路参数对短路损耗和结温分布的影响.理论与实验结果表明,SiC MOSFET串联短路分压特性对电路参数具有较高敏感度,漏极电压与漏极电流不平衡动态变化会改变器件短路损耗,进而影响结温温升,造成串联短路SiC MOSFET不稳定变化.     

SiC MOSFET在航空静止变流器中的应用研究

航空静止变流器实现机载直流电到交流电的转换,对功率密度、效率、环境适应性、可靠性和电气性能等有较高的要求。碳化硅(SiC)半导体器件的开关速度快、高温特性好,在航空静止变流器中有很好的应用前景,但目前关于宽禁带器件在航空静止变流器中应用的研究比较少。首先结合现有的典型航空静止变流器电路拓扑分析了SiC MOSFET应用的关键问题;然后针对航空静止变流器逆变级的两级级联半桥逆变器,对比分析了应用SiC MOSFET与Si MOSFET的损耗大小,分析结果表明在现采用的开关频率下,即使现有SiC MOSFET导通损耗较大,但总损耗仍较小;且开关频率越高,SiC MOSFET的效率优势越明显,最后为适应高开关频率SiC MOSFET逆变器的需要设计了一种适应高开关频率和宽占空比变化信号的SiC MOSFET驱动电路,搭建了1台500 VA、115 V/400 Hz两级级联半桥逆变器实验样机,并验证了应用SiC MOSFET的航空静止变流器逆变级的可行性。     

压接式SiC MOSFET模块

本文介绍了一种适用于SiC MOSFET的压接式封装方法。针对SiC MOSFET芯片面积较小的特点,使用弹性压针实现SiC MOSFET芯片上表面的压力接触。由于散热器同时也是电流通路,为减小由散热器引入的寄生电感,采用了一种厚度较薄且具有良好散热性能的微通道散热器。本文介绍了研制的压接式SiC MOSFET样品。通过仿真和实验评估了样品的电、热特性,验证了所提出封装方案的可行性。     

一种包含物理效应的SiC MOSFET行为模型

建立了一种基于PSpice的碳化硅金属-氧化物半导体场效应晶体管(SiC MOSFET)行为模型,该模型采用非分段方程拟合器件静态I-U特性和动态C-U特性。通过在模型中引入数学修正项,展现了相关物理效应和温度对器件特性的影响。提出了一种参数提取流程,模型参数提取所用器件测试数据通过SiC MOSFET商用数据手册获得,不需要进行复杂的器件特性测试实验,简化了建模流程。最终通过仿真和双脉冲测试验证了模型的静态和动态特性。结果表明,该模型在预测SiC MOSFET器件行为方面具有足够的精度和效率,为功率变换电路设计提供了一个实用的仿真模型。     

驱动回路参数对碳化硅MOSFET开关瞬态过程的影响

在电力电子系统中,碳化硅(Si C)MOSFET的开关特性易受系统杂散参数的影响,表现为电磁能量脉冲形态属性的非理想特性,并进一步影响系统效率和可靠性。针对Si C MOSFET,首先分析控制脉冲、驱动脉冲及电磁能量脉冲三者间形态属性的关系,提取影响Si C MOSFET开关瞬态过程的关键参数,即开关过程中的dv/dt和di/dt。基于Si C MOSFET的开关过程,分析驱动回路参数对dv/dt和di/dt的影响,并通过PSpice仿真及搭建Si C MOSFET双脉冲测试实验平台进行分析和比较。在此基础上,对基于驱动回路参数的瞬态控制方法进行对比分析,为实际应用中对Si C MOSFET的开关特性改善提供重要的理论基础。     

Study of Electron Transport in SOI MOSFETs Using Monte Carlo Technique with Full-Band Modeling

Effects of conduction-band non-parabolicity on electron transport properties in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) are studied by performing Monte Carlo simulation with a full-band modeling. An empirical pseudo-potential method is adopted for evaluating the two-dimensional electronic states in SOI MOSFETs. SOI-film thickness dependence of phonon-limited mobility, drift-velocity and subband occupancy is calculated and the results are compared with those of a simple effective mass approximation. The non-parabolicity effects are found to play an important role in 4-fold valleys under higher applied electric fields or at higher temperatures.     

基于SiC MOSFET的辅助变流器应用研究

辅助变流器是轨道交通车辆的重要部件,采用SiC MOSFET作为开关器件能整体提升变流器功率密度。将原有变流器系统完成以SiC MOSFET为开关器件的功率模块整体替代,对周边无源器件进行优化设计;根据SiC MOSFET器件特性设计一款驱动电路,并进行性能测试;针对辅助变流器主电路拓扑,建立各部分损耗模型,通过仿真进行验证,并对前后系统进行损耗对比。     

An Improved Energy Transport Model Suitable for Simulation of Partially Depleted SOI MOSFETs

When applied to partially depleted SOI MOSFETs, the energy transport model predicts anomalous output characteristics. The effect that the drain current reaches a maximum and then decreases is peculiar to the energy transport model. It is not present in drift-diffusion simulations and its occurrence in measurements is questionable. The effect is due to an overestimation of the diffusion of channel hot carriers into the floating body. A modified energy transport model is proposed which describes hot carrier diffusion more realisticly and allows for proper simulation of SOI MOSFETs.     

Analysis of nonequilibrium phenomena on electric characteristics of advanced MOSFETs by using a quantum energy transport model

In this paper, we have investigated nonequilibrium effects for advanced MOSFETs by using a device simulator with quantum energy transport (QET) model. The QET model allows to simulate nonequilibrium carrier transport as well as quantum confinement. The QET model includes the mobility model as a function of carrier temperature in order to consider the nonlocal effects. We have simulated advanced MOSFETs down to 20 nm gate length using the QET model. The QET model is compared with the quantum drift diffusion (QDD) model which includes a mobility model with local assumptions. It is found that the nonlocal mobility model is needed to simulate the advanced MOSFETs with less than 40 nm.     

Modified octree mesh generation for Manhattan type structures with narrow layers applied to semiconductor devices

One of the most important steps in the process of semiconductor device simulation, or any other numerical simulation based on finite elements, finite differences or similar standard techniques, is the discretization of the domain of the problem. A mesh must be generated, and its properties determine the stability of the numerical solver, computational time and quality of the solution. In this paper an octree‐based mesh generator is presented. The classical model for octree generation have been modified to optimize the programme for special regions of interest in the semiconductor device problem, Manhattan structures with very narrow layers. Using this technique, several meshing patterns have been tested and compared. Numerical results of the generation of general meshes are presented to demonstrate the efficiency of the algorithms from two points of view: mesh quality and computational effort. It has been successfully applied to the modelling and simulation of different transistors, High Electron Mobilty Transistors (HEMTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Copyright © 2006 John Wiley & Sons, Ltd.     

A design of MOSFET‐C impedance simulation circuits based on a GIC

This paper proposes a systematic design method of MOSFET‐C impedance simulation circuits based on a generalized immittance converter (GIC). The design method can realize inductance simulation circuits, capacitance multipliers and frequency‐dependent negative resistances (FDNRs) only by MOSFETs, capacitors and two operational amplifiers. Although MOSFETs are used instead of passive resistors, the realized impedance simulation circuits have good linearity since the nonlinearity caused by MOSFETs are cancelled out. The proposed design method derives three inductance simulation circuits, five capacitance multipliers and two FDNRs systematically from a GIC. All of them are summarized in this paper. As an example, inductance simulation circuits are designed by using the proposed design method. The inductance simulation circuits are applied to a filter realization and validity of the design method is confirmed by HSPICE simulations. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices

As MOSFETs are scaled to sub 100 nm dimensions, quantum mechanical confinement in the direction normal to the silicon dioxide interface and tunnelling (through the gate oxide, band-to-band and from source-to-drain) start to strongly affect their characteristics. Recently it has been demonstrated that first order quantum corrections can be successfully introduced in self-consistent drift diffusion-type models using Quantum Potentials. In this paper we describe the introduction of such quantum corrections within a full 3D drift diffusion simulation framework. We compare the two most popular quantum potential techniques: density gradient and the effective potential approaches, in terms of their justification, accuracy and computational efficiency. The usefulness of their 3D implementation is demonstrated with examples of statistical simulations of intrinsic fluctuation effects in decanano MOSFETs introduced by discrete random dopants. We also discuss the capability of the density gradient formalism to handle direct source-to-drain tunnelling in sub 10 nm double-gate MOSFETS, illustrated in comparison with Non-Equilibrium Green's Functions simulations.     

功率MOSFET抗SEB能力的二维数值模拟

在分析了单粒子烧毁(SEB)物理机制及相应仿真模型的基础上,研究了无缓冲层MOSFET准静态击穿特性曲线,明确了影响器件抗SEB能力的参数及决定因素.仿真研究了单缓冲层结构MOSFET,表明低掺杂缓冲层可提高器件负阻转折临界电流,高掺杂缓冲层可改善器件二次击穿电压,据此提出一种多缓冲层结构,通过优化掺杂浓度和厚度,使器...     

200°C operation of a 500-W DC-DC converter utilizing powerMOSFETs

This paper presents results from the operation of the power stage of a 500-W DC-DC converter at an ambient temperature of 200°C. This converter is designed to provide an output voltage of 12-Vdc from a 28-Vdc input. It utilizes an H-bridge configuration composed of eight International Rectifier power MOSFETs (parallel connections of two MOSFETs) and four Motorola diodes to convert the DC input voltage to a high-frequency square wave which can then be stepped up with a transformer. The transformer output voltage is then rectified and filtered to produce the DC output voltage. A phase-shifted pulse-width modulation (PWM) switching scheme is utilized to control the MOSFETs in the H bridge. This scheme allows zero-voltage turn-on of the MOSFETs to improve the efficiency. The efficiency of this converter when operated on the laboratory bench was measured to be 89%. The H bridge and transformer were then placed in an oven and operated over an ambient temperature range of 20°C-200°C. The efficiency varied from 86.1% to 85.4% over this temperature range. The long feedthroughs for oven operation caused the efficiency to decrease from 89% to 86.1%