500 MS/s 12位流水线ADC的设计研究

在超高速高精度模数转换器(ADC)设计中,低压运算放大器及其数字辅助校准算法至关重要。基于40 nm CMOS工艺、工作电压1.1 V,设计了一款500 MS/s、12位流水线ADC。系统采用前端无采保结构及低压级间运算放大器以降低系统功耗。本文提出了一种基于数字检测的算法校准级间增益和电容失配误差,使用较小的面积和功耗有效提高了ADC的整体性能。本数字校准方案将ADC的差分非线性(DNL)和积分非线性(INL)从2.4 LSB和5.9 LSB降低为1.7 LSB和0.8 LSB。对于74.83 MHz的正弦信号,校准技术分别实现了63.14 dB的信号-失真噪声比(SNDR)和75.14 dB的无杂散动态范围(SFDR),功耗为123 mW,满足设计指标,证明了带有数字校正的低压流水线ADC设计的有效性。     

一种低压低功耗Rail-to-Rail运算放大器的设计

基于TSMC 0.18μm互补型金属氧化物半导体(CMOS)工艺,设计了一种2 V低功耗恒定跨导Rail-to-Rail运算放大器。该运算放大器的输入级采用并行N沟道和P沟道差分输入级,实现了Rail-to-Rail的共模输入范围;为使输入跨导在整个共模输入范围内基本恒定,采用三倍电流镜技术;输出级采用带有Cascode米勒补偿的AB类输出控制电路。在Cadence Spectre环境下仿真后的结果显示:直流增益为91 dB,相位裕度为84.5°,单位增益带宽为9.4MHz,功耗为0.2 mW,适合应用在各种低压低功耗场合。     

德州仪器宣布推出最低功耗、最小尺寸的零漂移放大器

日前,德州仪器(TI)宣布推出最新系列的零漂移运算放大器,这些产品实现了高精度、微功耗以及微小型封装的完美组合。OPA333具有超低失调(2μV)、超低静态电流(17μA)、低至1.8 V的工作电压以及     

14位200MSPS三段式电流舵D/A转换器的设计

为满足现代通信系统和混合信号领域的要求,本文设计了一款14位、200MSPS的D/A转换器.通过对线性度、动态性能、功耗和面积的折中考虑并对二进制加权电流源与单位电流源的优化组合,设计采用了三段式电流舵结构.文中重点讨论了关键电路的设计,并基于SMIC 0.35μm Mixed Signal 2P3M工艺模型对电路进行了仿真验证.仿真结果表明D/A转换器的非线性误差和无杂散动态范围都达到了设计指标的要求.     

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

一种新型有源功率因数校正器的研制

介绍一种新型、基于有源开关或DC／DC变换技术的有源功率因数校正器：即新颖的Boost型有源功率因数校正器APFC（Active Power Factor Corrector)校正电路。给出Boost型APFC方案的主电路结构。重点分析了平均电流控制的CCM电路工作原理，对其功率因数校正过程作了详细的分析。并用Pspice软件进行仿真优化。给出了校正过程中电感电流各相关点波形。通过自行设计制作的450W实验样机进行验证，含有APFC电路与传统PF电路相比，λ值由0.67提高为0.98以上。仿真和实验结果说明了分析和设计的正确性。     

A 12‐bit multi‐channel dual‐mode successive approximation ADC for power management bus (Pmbus) devices

In this paper, a 12‐bit multi‐channel dual‐mode successive approximation ADC for PMBus devices is newly proposed. The proposed data converter is attractive because all the requirements of PMBus devices, which are high resolution, low‐cost, dual‐mode, and multi‐channel, are successfully matched. In measurement results, all the functions and performance of the proposed data converter are successfully verified and confirmed to be applied on PMBus devices. The area of this chip is 1.64 × 1.56 mm², and the measured power consumption including digital output buffers is 1.683 mW. The proposed 12‐bit multi‐channel dual‐mode successive approximation ADC is suitable for power monitoring systems, such as PMBus devices. Copyright © 2011 John Wiley & Sons, Ltd.     

鄂西电网功率振荡试验研究与治理

针对湖北电网本身及存在的问题，通过不同运行方式的计算机仿真，找出了鄂西地区功率振荡的原因，提出了应在相关机组上加装PSS装置的具体解决措施，现场实施后，抑制鄂西功率振荡的效果显著，恩施水电外送能力显著增加，取得了较好的社会效益和经济效益。     

Analysis and implementation of a step–up power converter with input current ripple cancelation

This paper proposes a power electronics converter capable of canceling the input current ripple at preselected duty cycle. The proposed converter is an extended topology of a buck–boost converter aided by a boost‐type converter that improves the quality of the current drawn from the direct current source. The voltage gain of the proposed converter is increased as well, with a minimum of extra component added to the original buck–boost power converter. These features make the proposed converter ideal for low voltage generation sources, such as photovoltaic panel and fuel cell applications. Along this paper, the state space mathematical model is developed to provide the key design guidelines. The theoretical analysis is validated through computer simulation and hardware prototyping.     

Power‐efficient burst‐mode RF transmitter based on reference‐adaptive multilevel pulse‐width modulation

Burst‐mode operation of power amplifier (PA) based on multilevel pulse‐width modulation (MPWM) has been frequently discussed as a potential solution to achieve higher efficiency in radio frequency (RF) transmitters. In this paper, a novel multilevel PWM modulator is proposed that utilizes adaptive triangular reference waveforms. As compared with conventional MPWM modulators, the proposed architecture provides significant wider design space such that the efficiency of system can be effectively optimized. A general transmitter architecture based on the proposed concept is analyzed in terms of power efficiency. Efficiency optimization procedures are presented according to input magnitude statistics. Based on the proposed modulator, an optimized 2.4‐GHz RF transmitter is designed in a 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. The circuit‐level simulations show that it delivers 25.8‐dBm peak output power with 46.1% peak efficiency. For a 20‐MHz worldwide interoperability for microwave access (WiMAX) signal with 8.5‐dB peak‐to‐average‐power ratio (PAPR), this transmitter achieves 28.8% (average) efficiency at 17.3‐dBm (average) output power with an error vector magnitude (EVM) of 2.97% rms.     

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

The switched‐current (SI) technique permits realizing analog discrete‐time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented. It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35µm CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35µm CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first‐order filter is built with the use of elementary cells on the chip. Copyright © 2008 John Wiley & Sons, Ltd.     

燃料电池并联供电系统的建模和控制

对燃料电池并联供电系统的数学模型建立过程和控制策略进行了研究。根据电路的工作原理,以电路中电感的电流和电容两端的电压为变量,推导出系统稳态状态空间的矩阵方程,进而建立主电路的小信号数学模型。在建立单个燃料电池供电的电压控制模型和稳定性分析之后,以平均电流法构建出整个系统的控制模型。通过分析闭环传递函数的幅频特性,对系统的稳定性进行了判定。在理论分析的基础上,对2台燃料电池并联供电系统及其控制方案进行了闭环仿真,给出了仿真输出波形。结果证明,所采用的分析方法和建立的数学模型以及采取的控制策略是正确的。     

抽水蓄能机组全工况试验条件下最大进相能力分析

依据同步发电机进相试验导则,提出了计及发电机功角、定子电流和机端电压三大约束因素的抽水蓄能机组最大进相能力计算方法,全面分析了发电和抽水工况下机组的最大进相能力,研究了升压变分接头档位对全工况试验条件下机组最大进相能力的影响。以洪屏抽蓄电站#1机组为算例,绘制了机组最大进相能力随系统电压和有功出力变化的Q-PV三维曲面,任意进相试验工况下机组的最大进相能力均能与曲面中的某点相对应。试验人员通过查表即可准确掌握机组全工况下的最大进相能力,并了解当前进相深度是否满足试验要求,大大提高试验机组最大进相能力评估的准确性。试验实测数据与理论计算结果基本一致,验证了所提分析方法的正确性和实用性。     

基于SEPIC变换器的高功率因数LED照明电源设计

针对LED驱动电源功率因数低的问题,依据LED照明电源的特点,选择SEPIC电路作为主电路拓扑实现功率因数校正(PFC)和LED电流控制。传统的SEPIC电路用于功率因数校正时都工作在断续模式下,通过对SEPIC电路的分析,证明了临界连续模式下SEPIC电路也可以实现PFC,并推导出输入输出电压比和功率因数关系的公式,得出当输入输出电压比很小时,功率因数值很高。该电源用单级电路同时实现功率因数校正和LED电流控制,相对两级功率因数校正电路,所用器件少,损耗低,尺寸小,尤其适合空间狭小的照明电源电路。通过实验证明理论分析的正确性。