A multipurpose circuit to read out and digitize pixel signal for low-power CMOS imagers

A complementary metal oxide semiconductor (CMOS) image sensor with a resolution of 128 × 128 pixels is presented in this paper in which pixel signal readout, noise suppression, and comparing operations are performed by one circuit during two steps: reading and conversion. The main idea of this work is to combine three main operations of an image sensor in one circuit. This method helps to decrease power consumption, silicon area, total noise, and imaging time. The total power consumption of the imager is 11 mW with a 2.5-V power supply and 40-fps frame rate. The pixel layout size is 10 × 10 μm² with a fill-factor of 81%. The analog to digital converter (ADC) resolution is 10 bits, and the error resulted from the proposed circuit is about ±0.5 least significant bit (LSB). The proposed CMOS image sensor was designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm CMOS technology and was simulated by CADENCE SPECTRE circuit simulator. This circuit can be proposed for a CMOS imager with highly accurate and efficient power consumption.     

Fractional charge packet counting with constant relative resolution

A charge‐to‐digital converter concept suitable for pixel‐level charge sensitive amplifiers is presented. The circuit implements a technique referred here as fractional charge packet counting, which ensures large dynamic range operation using constant integration time. By means of a particular circuit arrangement a constant number of significant bits is provided as output, thus ensuring a constant relative resolution over the entire dynamic range. A circuit implementing the concepts described above has been designed and simulated. Each block of the circuit is described in details and its characterization is presented. The circuit is capable to convert input currents in the range of 100 fA to 100 nA at 2 ksample/s with a constant resolution of 10 bit without the need of gain switching. Copyright © 2010 John Wiley & Sons, Ltd.     

Asynchronous demodulation technique for use in vision sensor image classification and segmentation

This paper presents a novel technique for classification and segmentation of a multiple‐object image scene. Each object in the scene is tagged by a flashing LED operating at a specific frequency. The vision sensor, based on this technique, demodulates the captured light signal, omits the background illumination, and performs classification by assigning a unique ID‐tag to each region based on its flashing light frequency. The process is performed in‐pixel by an asynchronous demodulation and frequency identification circuit, which is designed in a standard 0.6µm CMOS technology. Simulation results confirm the validity of the proposed structure. At a frame rate of 250 fps the power consumption is 2.6µW/pixel, which is relatively low compared with those of sensors with similar functionality. The structure is intended for use as a low power, inexpensive solution in robot visual position feedback and localization. Copyright © 2009 John Wiley & Sons, Ltd.     

A single‐stage LED streetlight driver with PFC and digital PWM dimming capability

This paper proposes a single‐stage light‐emitting diode (LED) driver that offers power‐factor correction and digital pulse–width modulation (PWM) dimming capability for streetlight applications. The presented LED streetlight driver integrates an alternating current–direct current (AC–DC) converter with coupled inductors and a half‐bridge‐type LLC DC–DC resonant converter into a single‐stage circuit topology. The sub‐circuit of the AC–DC converter with coupled inductors is designed to be operated in discontinuous‐conduction mode for achieving input‐current shaping. Zero‐voltage switching of two active power switches and zero‐current switching of two output‐rectifier diodes in the presented LED driver decrease the switching losses; thus, the circuit efficiency is increased. A prototype driver for powering a 144‐W‐rated LED streetlight module with input utility‐line voltages ranging from 100 to 120 V is implemented and tested. The proposed streetlight driver features cost‐effectiveness, high circuit efficiency, high power factor, low levels of input‐current harmonics, and a digital PWM dimming capability ranging from 20% to 100% output rated LED power, which is fulfilled by a micro‐controller. Satisfying experimental results, including dimming tests, verify the feasibility of the proposed LED streetlight driver. Copyright © 2016 John Wiley & Sons, Ltd.     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

This paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

Performance of a Zero Average Dynamics‐controlled buck converter using different pulse‐width modulation schemes

The response of a digital Zero Average Dynamics (ZAD)‐controlled buck converter under the variation of its intrinsic parameters as well as the pulse‐width modulation signal is studied in detail. The multiparameter analysis presented here leads to a complete knowledge of the different dynamical scenarios exhibited by the system. Numerical results indicate that the success of the ZAD‐strategy is highly dependent on the parameter and pulse‐width modulation (PWM) combinations. Experiments are included to validate the performance inside the so‐called optimum region. Copyright © 2013 John Wiley & Sons, Ltd.     

基于TMS320F240及IPM的新型通用变频器

介绍了一种全数字化高性能通用变频器。该变频器以空间矢量脉宽调制（SVPWM）技术作为理论基础，以电机控制专用芯片TMS320F240作为控制核心，采用智能功率模块（IPM）作为功率元件，组成交－直－交电压型逆变主回路。通过对数字信号处理器（DSP）的编程，实现用软件取代模拟器件进行高性能交流传动控制。利用与IBM－PC的串行异步通信，可以方便地设置各项参数，并同时完成采样、内部查表、输出模拟信号，具有控制外部电路等功能。测试结果表明，该变频器具有优良的动态和静态性能。     

Design and modeling of compliant micromechanism for mechanical digital‐to‐analog conversion of displacement

A microelectromechanical digital‐to‐analog converter (MEMDAC) converts digital motion of shuttle actuators operated by the corresponding bits of a binary code into an output displacement proportional to the analog value represented by the input code. In this paper a MEMDAC with improved kinematic design is devised that allows large travel range and high positioning resolution while making the microfabrication process less critical. A lumped‐parameter model of the compliant mechanism of an N‐bit MEMDAC is derived and used to determine the stiffness ratio of flexible members needed for proper mechanical digital‐to‐analog conversion. Furthermore, we analytically investigated the effect of nonuniformity in the device geometry due to the limitations of the microfabrication processes on the linearity of the output displacement. Successful fabrication and release of a 12‐bit MEMDAC demonstrated the manufacturability of the new mechanism, revealing opportunities for MEMS applications in which micropositioners with open‐loop operation, relatively large output range, fine positioning resolution and high repeatability are required. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Meeting the analog world challenge. Nyquist-rate analog-to-digitalconverter architectures

To bring digital processing and its benefits to bear on real-world applications, the analog signal of interest must be translated into a format a digital computer can utilize. This is the function of the analog-to-digital converter (ADC). After processing by a digital computer or digital signal processor (DSP), the resulting digital stream of information must be returned to its analog form by a digital-to-analog converter (DAC). The methods by which a digital code is generated within the ADC are diverse. We introduce three popular Nyquist-rate ADC architectures used today: the counter ramp ADC, the successive approximation ADC and the flash ADC     

Characteristics of a two‐dimensional integrated magnetic sensor for position sensing and motor control

Two‐dimensional integrated magnetic sensors for position sensing were designed and fabricated with the standard 0.35‐µm CMOS process on silicon. One such type is the n‐type Hall sensor that uses an inversion layer under the gate oxide of the MOSFET. The Hall sensors were arrayed (64 × 64), and the control digital circuits and output amplifier were also integrated into the same chip. ‘One pixel’ was 50 × 50 µm, and the entire chip was 4.9 × 4.9 mm. The sensitivity of one of these sensors was 2.7 mV/(mA·kG). The two‐dimensional magnetic flux distribution was measured from the 5‐mm diameter Nd–Fe–B rare‐earth permanent magnet. About 42 s was required to measure one frame. The position of the magnet could be detected with the fabricated sensors. Magnetic sensors using an inversion layer in MOSFETs are useful for position sensing systems, but their noise characteristics, such as poor sensitivity, should be improved. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

A very low complexity impulse radio‐ultrawideband (IR‐UWB) transmitter suitable for balanced antenna is presented. This all‐digital transmitter employs the binary phase‐shift keying (BPSK) modulation scheme and eliminates the need for a balun. Also, a new Gaussian monocycle pulse generator is proposed which is used as impulse transmitted signal. The transmitter circuit was designed in 0.18‐μm complementary metal–oxide–semiconductor technology. The post‐simulation results show that the core chip size was only 0.02 mm². The output amplitude pulse yielded 150 mV peak‐to‐peak under a supply voltage of 1.8 V. Simulation results show that the transmitter consumes 8.5 pJ/pulse for 200‐MHz pulse repeating frequency. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A compact CMOS DC-DC buck converter based on a novel complement value leaping PWM technique

A very compact ultra-low power DC-DC buck converter is presented. The proposed buck converter employs a novel complement value leaping pulse-width modulation (PWM) technique to realize the desired DC mean-value for various loads. Incorporating just two counters with a simple digital controller to load the repeatedly complemented value of the 4bit up/down counter as the initial value of the least significant bits of the 5bit up counter, a PWM pulse is created to manage the charge/recharge period. The realized PWM signal maintains the same desired output voltage mean value for any load resistance between 80 and 140 Ω. The switching frequency is 160 kHz, and the overall power consumption is 26.9 nW, while the efficiency is 93.4% for current range of 1.7 to 3 mA. The performance of the proposed converter is validated by Cadence post-layout simulations utilizing TSMC180nm CMOS technology for 1-V supply voltage providing the output voltage mean value of 0.24 V.     

新型直接数字转换器设计与分析

为了在电阻式传感器输出与数字仪器输入之间建立数据接口,设计了新型直接数字转换器。该转换器采用双斜式变换原理,可以使单端电阻传感器直接输出数字信号。分析表明,对于非理想因素引起的转换器增益误差和偏置误差,可以通过增益修正及偏置补偿方法消除。该转换器具有结构简单、易小型化、稳定性好、可靠性高的特点。实验结果显示了该转换器具有良好的线性,在整个测量范围内,最大误差小于0．25%。     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

Pulsed time‐of‐flight pixel with on‐chip 20 klux background light suppression in standard CMOS technology

A novel time‐of‐flight pixel designed in 0.18‐μm standard CMOS technology with an indirect pulsed technique is presented. This design is capable of operating in ambients with high levels of background light, since a novel in‐pixel background suppression circuit makes it robust up to 20 klux of ambient light. In addition to this, the pixel incorporates an adaptive number of accumulations circuit that selects the optimum number of accumulations for each situation at pixel level, avoiding saturation even under high illumination conditions.     

CMOS current‐steering DAC architectures based on the triple‐tail cell

In this paper two novel current‐steering digital‐to‐analog converter (DAC) architectures, exploiting the triple‐tail cell as switching element, are presented. The proposed solutions are theoretically analysed and design equations are carried out. The two architectures show better performance than the classical binary‐weighted solution and it is shown that they can profitably substitute the binary sub‐DAC section in a segmented topology. Theoretical results are compared with behavioural‐level simulations and confirm the effectiveness of the proposed architectures. Copyright © 2007 John Wiley & Sons, Ltd.     

A step‐up PWM DC–DC converter for renewable energy applications

A step‐up pulse width modulation (PWM) direct current (DC)–DC converter is presented in this paper, which has its origin in quasi Z‐source inverter. Analysis of this converter in steady state is presented, and relevant expressions are derived for the proposed converter operating in continuous conduction mode. The power loss expressions for each component of the converter are derived, and thereby, obtained expressions for overall converter efficiency are presented. Further, a dynamic model is derived to design an appropriate controller for this converter. The simulation and experimental results are presented to support the theoretical analysis. The advantages such as continuous input current, high step‐up gain at lower duty ratio, and common ground for source, load, and switch makes the converter suitable for renewable energy applications. Copyright © 2015 John Wiley & Sons, Ltd.