基于GPR的变工况下闭环SEPIC的故障预测

变工况下闭环单端初级电感变换器(SEPIC)系统级的故障预测,不仅受故障模式的影响,还受工况变化的影响。针对此问题,采用了一种新颖的变工况下闭环SEPIC变换器系统级故障特征参数(S-FCP)的提取方法,并提出了一种基于高斯过程回归(GPR)对S-FCP退化状态预测的方法。首先,研究了在不同工况下闭环SEPIC变换器关键元件的退化对系统级参数的影响。其次,选取对关键元件退化敏感且退化趋势有规律的系统级参数作为闭环SEPIC变换器的S-FCP,并利用多元最小二乘回归得到额定工况下的S-FCP。最后,基于GPR对S-FCP进行故障预测,实现变工况下闭环SEPIC变换器的故障预测。实验结果证明了该S-FCP提取方法和预测框架的可行性。     

Junction leakage current degradation under the off-statebias-temperature stress: a new reliability assessment method forhigh-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed     

固体氧化物燃料电池失效快速判断机理探讨

在简单综述了导致固体氧化物燃料电池(Solid Oxide Fuel Cell,SOFC)失效的主要原因的基础上,探讨了采用实验室模拟加速的实验研究和材料损伤演化动力学与计算机模拟的理论研究来对SOFC的失效进行快速判断的可行性。     

Stress voltage polarity dependence of JVD-Si/sub 3/N/sub 4/ MNSFET degradation

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.     

An online groundwall and phase-to-phase insulation quality assessment technique for AC-machine stator windings

An online technique for monitoring the condition of the groundwall (GW) and phase-to-phase (PP) insulation for three-phase ac-machine stator windings is proposed in this paper. Insulation-condition indicators such as capacitance, dissipation factor (tan/spl delta/), and ac insulation resistance are calculated online based on the differential leakage-current measurements for each phase. A model for a three-phase ac-machine insulation system is derived and analyzed for both offline and online testing. Guidelines for interpreting the measured indicators for determining the: 1) overall condition and 2) significant degradation in the individual GW and PP insulation for each phase of the stator are given based on the analysis. Experimental results on a 15-hp induction motor under intentional GW and PP insulation degradation conditions show that incipient insulation degradation can be detected and classified with high sensitivity.     

Quantifying the nature of hot carrier degradation in the spacerregion of LDD nMOSFETs

A detailed quantitative analysis of the hot carrier degradation in the spacer region of LDD nMOSFETs using stress conditions for maximum hole (V_g ~ V_t), substrate (I_submax) and electron (V_g = V_d) current from microseconds is presented. Damage in the spacer region reveals a two-stage drain series resistance degradation with an early stage lasting about 100 ms. The nature of damage is investigated by alternate electron, hole injection, and charge pumping measurements. It is seen that the hot carrier damage in the spacer oxide in the early stage is dominated by interface state creation with no evidence of significant damage by trapping mechanism either by electrons or holes. These results are in contrast to degradation behavior in the channel region where damage by trapping is a well-established mechanism of degradation under electron or hole injection     

航天继电器贮存过程吸合时间退化机理研究

航天继电器作为一种密封的电器元件,其贮存可靠性对于导弹等武器装备至关重要。如何测试评价航天继电器在贮存过程中性能及可靠性的衰退,是继电器用户和厂家非常关心的问题。利用开发的实验系统对某型号航天继电器进行了贮存加速实验,得到了吸合时间的变化规律。分析并验证了贮存过程中吸合时间变化的主要原因是簧片应力松弛所导致的反力变化。通过仿真与实验均证实了吸合时间与簧片初力存在近似的线性关系,进而提出可采用吸合时间来表征簧片的应力松弛退化特性。建立了高温条件下继电器吸合时间的贮存退化模型,为进一步研究继电器贮存可靠性及贮存寿命预测奠定了基础。     

基于决策树的光伏组件故障诊断方法研究

分析了光伏组件在局部阴影或异常老化状态下的输出特性,提出了一种基于决策树算法的光伏组件在线诊断局部阴影或异常老化的判断方法。同时分析了在这两种状态下填充因子FF、斜率因子K和输出电流比Im/Isc的变化规律,结合光伏组件的四个输出参数(最大功率点电压Um和电流Im、开路电压Uoc和短路电流Is)一起作为属性集合,用于提供给决策树生成算法自由选择合适的属性生成故障诊断决策树。实际应用中,只要获得需要的属性数据即可通过生成的决策树诊断出光伏组件的工作状态。实验结果证明了该方法的可行性和有效性。     

检测XLPE电缆绝缘水树老化状态的超低频方波-工频叠加法研究

本文提出了能有效检测ＸＬＰＥ电缆绝缘水树老化状态的超低频方波－工频电压叠加法新技术,对含水树ＸＬＰＥ电缆分别放加单极性方波和正负对称方波电压叠加工频电压所产生的响应电流特性进行了实验研究,找出了最佳叠加工频电压值,最后对产生超低频方波－工频电压叠加电汉响应的机理及其检测的影响因素进行了探讨。     

Smart electricity meter reliability prediction based on accelerated degradation testing and modeling

The smart electricity meter (SEM) is one of the most critical elements of smart grids. The billing function of SEM is one of its most important functions to its operators and end-users. Because the SEM devices need to be highly reliable, in this study we conduct accelerated degradation tests (ADTs) for the prediction of SEM reliability with respect to the billing function. For designing the ADTs, we have identified five key modules and their components, two performance indicators, and three possible degradation stressors. Six ADTs are conducted under different configurations of the stressors. The test data are then used to fit degradation paths by linear regression models. Extrapolation to the failure threshold allows the prediction of the Time-to-Failure of SEM. Finally, the reliable lifetime of the SEM is predicted by an accelerated degradation function which is obtained by fitting a Weibull failure time distribution.     

Photocatalytic Degradation of MB with Yeast-supported ZnS Hybrid Microspheres

Yeast cells were utilized as novel bio-carriers in the synthesis of yeast/ZnS (YC/ZnS) composite microspheres in this paper. The as-produced particles are characterized by SEM, TEM and XRD. Employing the as-obtained YC/ZnS hybrid as new photocatalysts, we studied the main influencing factors in the photocatalytic degradation of low concentration methylene blue wastewater. The results indicated that the ZnS hybrid particles were of core-shell structure with the 450–500 nm shell of ZnS covering yeast carriers. In the degradation experiments, pH, dosage of YC/ZnS and UV illumination distance had significant influence on the degradation of methylene blue wastewater. The degradation rate reached 95.2% under the optimal conditions when 10 mg/L methylene blue aqueous solution was photocatalyzed with 3g/L YC/ZnS at pH8, 20–30°C and illumination distance 50 cm.     

基于导频序列的空时编码OFDM系统的信道估计方法

利用空时分组码(STBC)导频序列,在最小二乘(LS)和最小均方误差(MMSE)信道估计技术的基础上,用基于本征向量分解(EVD)的低秩信道估计技术对空时编码OFDM系统进行信道估计,避免了矩阵求逆运算,大大减少了运算量。分析并仿真了在降低秩条件下的系统性能和用不同调制结构的不同空时码的性能。仿真结果表明,降低秩会影响系统性能,当忽略掉一个相对较小的特征值时,系统性能降低较少;如果相对很重要的特征值被忽略,系统性能就会随信噪比的增大下降较多。系统性能会随空时码状态的提高和采用更高调制结构而提高。     

基于数据融合方法的智能电能表运行剩余寿命预测

本文融合加速退化试验数据和外场检测退化数据对智能电能表进行在线运行的剩余寿命预测。首先,基于加速退化试验（ADT）数据建立非线性Wiener过程退化模型和温湿综合加速模型,利用贝叶斯理论估计模型参数。其次,利用外场检测的退化数据对退化模型中参数进行不断更新,采用粒子滤波算法实现这一更新过程。最终,给出智能电能表在外场状态检测时刻开始的剩余寿命预测结果。该方法解决了两个问题,一是解决了仅仅利用ADT数据对智能电表在线运行状态评估不准确的问题;二是解决了仅仅利用外场使用条件下的数据量建立预测模型不准确的问题。不仅如此,使用粒子滤波（PF）算法对参数更新的精确度也很高。因此,本文对于智能电能表数据融合方法的研究有着一定的参考价值。     

基于复合核 SVM 的智能电表基本误差预测方法

智能电表作为电网的终端设备,其退化情况与工作环境、运行时间等因素密切相关.针对复杂变量条件下智能电表退化情况难以预测的问题,提出一种基于复合核支持向量机(support vector machine,SVM)的智能电表基本误差预测方法.首先对智能电表退化数据进行分析,采用皮尔逊相关性分析找出与智能电表基本误差相关性极强的环境变量.然后,为进一步提取数据退化特征,采用模糊C均值聚类算法对智能电表退化数据进行聚类,确定退化特征向量.最后,基于高斯径向基核函数与多项式核函数构造一种新的复合核SVM模型用以预测智能电表基本误差.结合新疆地区智能电表退化数据对复合核SVM模型性能进行验证,实验结果表明,复合核SVM模型可以准确预测复杂环境下智能电表的基本误差,其预测准确率高于贝叶斯方法、神经网络方法以及经典SVM方法.     

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current I_sub, which becomes increasingly problematic with technology scaling as various leakage components dominate I_sub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.     

Evaluation of Power Line Communication Equipment in Home Networks

In this paper, we examine the performance of power line communication equipments (ethernet-to-powerline adapters) that come from different vendors and are based on different technologies and standards. The scope is to investigate commercially available power line communications (PLC) equipment in their actual working environment under real conditions. Coexistence issues are studied, as well as the possible degradation of performance in case powerline adapters from different manufacturers and technologies are simultaneously operating in the powerline network under consideration. The influence of potential noise sources (ac adaptors, cell phone chargers), as well as plug-in cases that are not recommended by the manufacturers but are, however, convenient in domestic grids (power strips, extension cords), are also examined.     

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

Design for ASIC reliability for low-temperature applications

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges.     

基于体效应的SiC MOSFET器件栅极老化监测方法研究

长期以来,栅极老化一直是SiC MOSFET器件可靠性研究的关键,而偏置温度不稳定性则是栅极老化的重要现象。由于栅极老化的偏置温度不稳定性存在应力撤出后的恢复现象,如能在可靠性实验中快速、准确地监测SiC MOSFET器件的栅极老化变化量,对可靠性研究具有重要意义。因此,文中提出一种新的栅极老化监测方法。该方法以体效应下的阈值电压VTH(body)为基础,建立理论模型来描述VTH(body)和栅极老化之间的关系。提出在栅极电压开关过程中从体二极管电压–栅极电压曲线中得到VTH(body)的方法,并详细研究实验参数对VTH(body)的影响。此外,通过高温栅偏实验对VTH(body)的实用价值进行验证,并与栅极老化参数阈值电压VTH进行对比。实验结果证明,提出的新型栅极老化监测方法可以实现栅极老化的快速、准确及非恒温环境监测。     

High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides

In this paper, the authors investigate polysilicon gate MOS capacitors and MOSFET devices with nitrided oxides. These devices are known to also show a strong negative bias temperature instability (NBTI) effect. The authors analyze the dependence of oxide-trap generation in p-channel and n-channel devices on negative and positive Fowler-Nordheim (FN) charge injection stress by application of various C-V and charge pumping (CP) measurement methods yielding information on traps at different oxide locations. In the case of p-channel devices, a strong evidence for a preexistent very high oxide-trap concentration near the gate already before stress application is obtained. This feature is accompanied by a fast degradation of the p-channel devices under a negative bias stress similar to NBTI degradation. The CP measurements, which, in contrast to classical methods, are able to distinguish between actually fast interface traps and the slower near-interface oxide traps (NIOTs), showed that in all devices, a stress polarity dependence of trap generation occurs only for NIOTs and not for interface traps