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1.
The need to use 3D process simulation increases as device dimensions shrink and new 3D device designs emerge. Moreover, many state-of-the art CMOS devices employ some sort of stress engineering, which necessitates 3D stress simulations. To perform these simulations efficiently and quickly, new methodologies need to be employed. In this paper we demonstrate several applications of the next generation TCAD tools to 3D simulation problems critical for understanding and development of modern devices.  相似文献   

2.
We utilize a fully self-consistent quantum mechanical simulator based on CBR method to optimize 10 nm FinFET devices to meet ITRS projections for High Performance (HP) logic technology devices. Fin width, gate oxide thickness, and doping profiles are chosen to reflect realistic values. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using unstrained conventional (Si) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. In addition, small signal analysis has been performed. Sensitivity of device performance to the process variation at room temperature has also been investigated.  相似文献   

3.
Ultra-shallow Si p+n junctions formed by plasma doping are characterized by electrochemical capacitance-voltage (ECV). By comparing ECV results with those of secondary ion mass spectroscopy (SIMS), it is found that the dopant concentration profiles in heavily-doped p+ layer as well as junction depths measured by ECV are in good agreement with those measured by SIMS. However, the ECV measurement of dopant concentration in the underlying lightly doped n-type substrate is significantly influenced by the upper heavily-doped layer. The ECV technique is also easy to control and reproduce. The ECV results of ultra-shallow junctions (USJ) formed by plasma doping followed by different annealing processes show that ECV is capable of reliably characterizing a Si USJ with junction depth as low as 10 nm, and dopant concentration up to 1021 cm−3. Also, its depth resolution can be as fine as 1 nm. Therefore, it shows great potential in application for characterizing USJ in the sub-65 nm technology node CMOS devices. __________ Translated from Chinese Journal of Semiconductors, 2006, 27(11): 1966–1969 [译自: 半导体学报]  相似文献   

4.
This paper presents a novel low‐power CMOS extra low‐frequency (ELF) waveform generator based on an operational trans‐conductance amplifier (OTA). The generator has been designed and fabricated using 2.5‐V devices available in 130‐nm IBM CMOS technology with a ±1.2‐V voltage supply. Using the same topology, two sets of device dimensions and circuit components are designed and fabricated for comparing relative performance, silicon area and power dissipation. The first design consumes 691 μW, while the second design consumes 943 μW using the same voltage supply. This low‐power performance enables the circuit to be used in many micro‐power applications. ELF oscillation is achieved for the two designs being around 3.95 Hz and 3.90 Hz, respectively, with negligible waveform distortion. The measured frequencies agree well with the simulation results. The first design is found to provide overall optimal performance compared to the second design at the expense of higher silicon area. Copyright © 2015 John Wiley & Sons, Ltd.  相似文献   

5.
Negative Bias Temperature Instability (NBTI) is a critical reliability issue for CMOS technology, as this directly impacts the CMOS circuit performance parameters causing system failure. Moreover, NBTI behavior for radio frequency (RF) signals needs more understanding. On the device level, there has been much research on the relation between NBTI and RF. Many of those works contradict each other on the question of RF dependency with NBTI. Hence, the behavior of NBTI must be analyzed at the circuit level using a prediction technique. In this article, we analyzed the circuit level impact of NBTI for microwave frequency and developed a gain transformation technique for RF circuits in the microwave frequency range. To do this, we employed a 65 nm conventional ring oscillator as an RF block and carried out an aging simulation on it. A compatibility analysis was performed on low and high bandwidth microwave signals. The implemented statistical technique can determine the actual operable frequency range, so that the RF circuit can perform with minimal NBTI effect.  相似文献   

6.
This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.  相似文献   

7.
The importance of intrinsic fluctuations to the next generation of CMOS circuits has renewed interest in simplified, computationally inexpensive routes to the analysis of circuit parameters such as threshold voltage and subthreshold slope in ensembles of devices. A quasi-3D analytic approach to the statistical analysis of these parameters in 100 × 100 nm, 70 × 70 nm and 35 × 35 nm devices has been compared to the more computationally expensive full 3D simulation. The quasi-3D approach is useful in predicting variations in subthreshold slope, although its predictions become inaccurate for devices of approximately 35 × 35 nm or smaller. It is less effective in considering variations in threshold voltage, erroneously predicting a rise of the ensemble average threshold voltage and significantly exaggerating the threshold voltage variations over the ensemble.  相似文献   

8.
Physics-based simulation of single-event effects   总被引:1,自引:0,他引:1  
This paper reviews techniques for physics-based device-level simulation of single-event effects (SEEs) in Si microelectronic devices and integrated circuits. Issues for device modeling of SEE are discussed in the context of providing physical insight into mechanisms contributing to SEE as well as providing predictive capabilities for calculation of SEE rates. Recent advances in device simulation methodology are detailed, including full-cell simulations and cross-section calculations from first principles. Examples of the application of physics-based SEE simulations are presented, including scaling trends in soft error sensitivity as predicted by device simulation, single-event latchup (SEL) simulations in CMOS structures, and recent simulations of single-event transient (SET) production and propagation in digital logic circuits.  相似文献   

9.
In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of extension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.  相似文献   

10.
暂态稳定控制装置的测试与仿真浅析   总被引:4,自引:0,他引:4       下载免费PDF全文
针对稳定控制与继电保护装置在测试与仿真方面的较大差距 ,从国内暂态稳定控制测试装置的现状入题 ,分析了开发较为通用的稳定控制测试装置的意义与可能性 ,讨论了测试与仿真、诊断的关系 ,指出一般的稳定控制装置测试流程 ;而后分别具体介绍了稳定装置的模块测试、综合测试、数字仿真的方法以及用于稳定性判别的常见仿真软件 ,这些测试与仿真技术不仅在稳定控制领域 ,而且在继电保护与其它自动装置领域也有着同样重要的用途 ;最后作者指出了稳定控制测试与仿真技术在网络化、智能化、实时性、模块化等方面的发展趋势  相似文献   

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