冲击测量用数字记录仪校验系统的建立和应用

介绍了冲击测量用数字记录仪校验系统的组成、校验项目及方法,并给出了对Tek2440型数字记录仪校验的结果。结果表明,它能满足IEC标准的要求。     

瞬态数字记录仪与高压试验技术

数字记录仪已经成为一种有发展前途的测量仪器用在高压实验室中。本文讨论了快速数字记录仪的动态性能,论述了数字记录仪和数字技术在高压测试中的应用。     

高电压试验及测挝技术标准最新动态

国际电工委员会IEC42技术委员会近几年开始了新一轮标准制、修订,包括：IEC60060《高电压试验技术》、IEC61083《高电压冲击试验用数字记录仪》、IEC62475《大电流试验技术：试验电流和测量系统的定义和要求》和IEC60270《局部放电测量》等标准。介绍了高电压试验技术标准的制、修订内容：重新定义了叠加过冲或振荡的雷电击冲击参数并新增计算方法,雷电冲击限值提高到10％,增加了用于从以。计算试验电压的K。的重复计算程序;给出了高电压测量系统允许的测量总不确定度。新的大电流试验技术标准IEC62475则将直流、交流、冲击电流测量全部纳入,数字记录仪和测量软件标准我国2008年等同采用IEC61083_2制定了GB／T16896．2标准。最后还介绍了冲击电压标准测量系统和试验短路电流标准测量系统的国际比对情况,我国好几家单位都达到了标准要求。     

数字化测量雷电冲击波误差及波形平滑化处理

提出了数字式瞬态记录仪测量雷电冲击波头时由采样率及量化所产生误差的计算公式及减小误差的方法 ,讨论了波形平滑化处理方式并给出其计算方法     

用于高压试验室的数字脉冲记录仪

在高压试验室中,数字记录仪将逐步替代传统的脉冲示波器。本文介绍加拿大魁北克高压试验室使用数字记录仪的情况,以及他们为减小高压试区强电磁干扰的研究成果。     

数字记录仪冲击测量误差的计算

由于数字仪测量误差的随机性和非线性又由于冲击电压是快速一次暂态过程,这就使得数字仪冲击测量误差的计算变得异常困难,至今尚未有人能给出数字仪冲击测量误差普遍适用的计算方法。现推导了由数字仪的指数波响应求冲击响应的计算公式,从而解决了数字仪冲击测量误差理论计算的难题,文中计算并给出了390AD数字仪的冲击测量误差。     

冲击电压标准波源的研制

IEC标准规定使用高精度的冲击电压标准波源校准数字记录仪,为了能够校准冲击电阻分压器和数字记录仪组成的完整测量系统,文中介绍了可产生IEC 60060-1—2001中规定的雷电全波的冲击电压标准波源的原理、设计和结构。冲击电压标准波源为小型的MAX发生器,其电压峰值Up、波前时间T1、波尾时间T2都可以根据脉冲形成回路的元器件参数计算得到。该标准波源的输出电压波形峰值为80~1 000 V,理论计算时间参数(0.791/58.22)μs。采用PTB校准过的14Bit数字记录仪测量低阻抗标准的输出波形,电压峰值Up实际测量结果与设置值的偏差在0~0.8‰之间;波前时间T1的偏差-2‰~3‰之间;半峰值时间T2的偏差为-1‰~0.8‰之间,峰值参数满足±1‰的允许误差要求,时间参数均满足±1%的最大允许误差要求,连续重复20次,最大标准偏差为2.5×10-4,一年内各电压点的峰值长期稳定性在0.3‰内。该标准波源可作为冲击电压溯源过程中校准数字记录仪的主标准,校准电阻值为3.25 kΩ的冲击电阻分压器,校准分压比为93.42,结果与分压器频率响应试验结果一致,时间参数与MATLAB程序计算结果吻合,表明该低阻抗冲击电压标准波源也可校准电阻分压器。     

数字记录仪动态特性校准的新方法

在国际上首次提出了高速数字记录仪动态特性校准的新方法——指数波试验,其主要优点在于在一次试验中可同时进行动态特性校准和冲击刻度系数的校准,确定静态下输出数据的分布,并能获得数字仪冲击测量误差的信息。因此,指数波试验是综合数字仪现行的直流电压,正弦波、斜角波、方波和冲击波等试验的主要作用的多功能试验,为数字仪冲击测量误差的计算提供了重要依据。     

数字波形记录仪的动态特性和直方图试验

数字波形记录仪的动态性能可以用直方图试验来描述,通过直方图试验可以获得模数变换器在一定试验频率下的微分非线性和失码,增益和偏移误差,直方图试验将给出在一定频率下各输出码的码级宽度的非常有用的信息。     

多路数字语音记录仪

本文介绍一种多路数字语音记录仪的结构及其关键技术。该仪器基于PC机结构并融合了高速DSP技术和语音数字处理的研究成果     

多比特数字信号频率测量方法

文中提出一种可直接测量多比特数字信号频率的方法，叙述了基本原理及实施方法。此方法的特点是实施简单，成本低廉、精度高。当信号频率较高且量化的比特数较多时，上述优越性别明显。     

A comparison of spectrum estimation techniques for sensorless speeddetection in induction machines

This paper compares digital spectrum estimation techniques which can be used to extract speed information from rotor slot and eccentricity harmonics contained in the stator current. In previous work, speed-related current harmonics have been shown to improve the performance of existing back-EMF-based sensorless schemes, since these harmonics are parameter independent and exist at virtually any nonzero speed. Digital filtering, however, requires a minimum data sampling time in order to achieve the desired resolution. The contribution of this paper is to determine the optimal method for accurately extracting the speed-related harmonics in the least amount of time. Several digital signal processing algorithms are investigated, including the fast Fourier transform and other traditional methods, as well as parametric techniques which can provide improved spectrum estimation for short data records. Each approach is evaluated on the criteria of accuracy, robustness, and computation time given a short data record     

基于原对偶内点法的电压无功功率优化

文章以电压无功优化的二次规划模型为基础,对原对偶内点法进行了扩展,使之能处理电压无功优化控制中大量的不等式的约束。文章提出了一种壁垒参数的选取方法和控制计算步长的策略,并采用了一种有效的预测校正方法来提高算法的收敛性。     

基于MATLAB信号处理工具箱的数字滤波器设计与仿真

介绍了一种利用MATLAB信号处理工具箱(SignalProcessingToolbox)快速有效地设计由软件组成的常规数字滤波器的方法。给出了使用MATLAB语言进行程序设计和利用信号处理工具箱的FDATool工具进行界面设计的详细步骤。利用MATLAB设计滤波器,可以随时对比设计要求和滤波器特性调整参数,直观简便,极大地减轻了工作量,有利于滤波器设计的最优化。还介绍了如何利用MATLAB环境下的仿真软件Simulink对所设计的滤波器进行模拟仿真。     

DSP数字电压调节器参数在线调整

以实际系统的实施为背景,介绍了DSP数字电压调节器中参数在线调整的一种新颖、快捷的方法,即通过DSP和上位机串口通信,利用Delphi编制控制界面,同时采用EEPROM芯片,实现调节器参数在线调整、数据的实时存储。     

高精度智能压力传感器的系统设计

本系统CPU采用08051F350,利用其24位A／D转换功能,实现了高精度模拟量数据采集,采用ModBus总线协议与上位机进行通信,将采集到的数据转换成数字信号实时地上传给上位机,并接受来自上位机的数据,进行参数设定。     

OTA‐based transmission line model with variable parameters for analog power flow computation

Analog computation has some inherent benefits over traditional digital computation methods and fosters a continued interest in research, specifically in power systems, due to its associated strengths. Among these advantages are physically realizable solutions, much faster computation times and more accurate models. To realize an analog computation environment for power system analysis analog models and their circuit realizations are required. This paper focuses on the design, simulation and hardware verification of transmission line models with variable parameters for the purpose of analog power flow computation. Specifically, pi equivalent lumped parameter and distributed parameter transmission line models with parametric variation based on temperature and frequency are presented. Operational transconductance amplifiers (OTAs) are the primary circuit elements in the hardware designs and allow remote reconfigurability and variation of transmission line parameters via transconductance gain. Test results are presented from a hardware prototype, which was developed and tested based on the proposed analog line models. Copyright © 2008 John Wiley & Sons, Ltd.     

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and modeling of compliant micromechanism for mechanical digital‐to‐analog conversion of displacement

A microelectromechanical digital‐to‐analog converter (MEMDAC) converts digital motion of shuttle actuators operated by the corresponding bits of a binary code into an output displacement proportional to the analog value represented by the input code. In this paper a MEMDAC with improved kinematic design is devised that allows large travel range and high positioning resolution while making the microfabrication process less critical. A lumped‐parameter model of the compliant mechanism of an N‐bit MEMDAC is derived and used to determine the stiffness ratio of flexible members needed for proper mechanical digital‐to‐analog conversion. Furthermore, we analytically investigated the effect of nonuniformity in the device geometry due to the limitations of the microfabrication processes on the linearity of the output displacement. Successful fabrication and release of a 12‐bit MEMDAC demonstrated the manufacturability of the new mechanism, revealing opportunities for MEMS applications in which micropositioners with open‐loop operation, relatively large output range, fine positioning resolution and high repeatability are required. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

一种新型多路同步数据采集卡的设计与实现

介绍了一种用于故障录波的新型多路同步数据采集卡的原理和软硬件实现方法。该数据采集卡采用接受GPS触发方式,可实现24路信号的同步采样,采样速率为单通道最高为250ksps,采样精度为16位。该装置可以通过基于FPGA的硬件在系统可编程技术根据录波对象的不同而方便地管理采样通道,PCI总线接口保证了其实时性和通用性。