A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

This paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (t_ox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_{C_AVG}, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (T_{C_AVG} = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_DD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

Calculation of Direct Tunneling Current through Ultra-Thin Gate Oxides Using Complex Band Models For SiO2

We report the calculation of gate leakage currents through the ultra-thin gate oxides (2.6–3.4 nm) in MOSFETs. We simulate J-V characteristics for the direct tunneling of valence electrons and inversion layer holes, which are measured using a charge separation technique. A two-band model is employed to express the complex band structure of the gate oxide, and its validity is discussed by calculating the complex band structure of -cristobalite based on the second nearest neighbor sp ³ s* tight-binding scheme.     

Current Conduction and Dielectric Behavior of High k-Y2O3 Films Integrated with Si Using Chemical Vapor Deposition as a Gate Dielectric for Metal-Oxide-Semiconductor Devices

Integration of Y₂O₃ high-k thin film over Si as gate dielectric in high performance CMOS and high-density MOS memory storage capacitor devices is described. Y₂O₃ film growth by low-pressure chemical vapor deposition induces interfacial reactions and complex SiO_{2 – x} layer growth. It has a graded structure, in crystalline-SiO₂ form at Y₂O₃ side and amorphous SiO_{2 – x} form at Si side. MIS devices based on Y₂O₃/SiO₂-SiO_{2 – x} composite dielectric integrated with Si show high frequency C-V behavior indicative of inversion to accumulation changes in capacitance. Observed bi-directional hysterisis in C-V is detrimental to the functioning of storage capacitor in memory function. Detailed investigation of this effect led to understanding of gate bias controlled emission of carriers as responsible mechanism. Observed anomalous increase in inversion capacitance at low frequency is attributed to additional charges transferred from SiO_{2 – x}/Si interface states. Leakage current and injected charge carrier transport across bilayer interface is dominated by Poole-Frankel (PF) process at low fields and by Fowler-Nordhiem (FN) at high fields. This investigation provides a greater understanding of the complex nature of integration of Y₂O₃ films.     

On the impact of high-κ gate stacks on mobility: A Monte Carlo study including coupled SO phonon-plasmon scattering

HfO₂ based high-κ dielectrics are among the most likely candidates to replace SiO₂ and the currently favoured oxinitride in the next generation of MOSFETs. High-κ materials allow the use of a thicker gate dielectric, maintaining the gate capacitance at reduced gate leakage. However, they lead to mobility degradation due to among other factors the coupling of carriers to surface soft optical phonons. Comparing the vertical field dependence of the mobility for HfO₂ and SiO₂, the severe degradation in mobility in the presence of high-κ becomes evident. The introduction of a SiO₂ interfacial layer between the channel and the HfO₂ mitigates the interaction with the SO phonons, but increases the equivalent oxide thickness (EOT) of the gate dielectric. The material of choice for the first commercial introduction of high-κ gate stacks is Hafnium Silicate (Si _x Hf_1-x O₂). This alloy stands up better to the processing challenges and as a result suffers less from dielectric fluctuations.     

PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract

The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO₂ buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity of the semiconductor was the same as that expected for ferroelectric switching.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Tunneling through Thin Oxides—New Insights from Microscopic Calculations

In this paper, we summarize our recent efforts to analyze transmission probabilities of extremely thin SiO₂ gate oxides using microscopic models of Si[100]-SiO₂-Si[100] heterojunctions. We predict energy-dependent tunneling masses and their influence on transmission coefficients, discuss tunneling probabilities and analyze effects arising from the violation of parallel momentum conservation. As an application of the present method, gate currents in short bulk MOSFETs are calculated, including elastic defect-assisted contributions.     

Fabrication and evaluation of LaCrO3 thin film heaters

Lanthanum chromium oxide (LaCrO₃) has excellent high‐temperature properties. LaCrO₃ doped with alkaline earth metals also has high electric conductivity. The purpose of this study is to fabricate thin film heaters using LaCrO₃ doped with Ca by RF magnetron sputtering method. The crystal structure of thin films was evaluated and the surface form was studied. The results show that the thin film deposited on Si(100) single crystal and quartz glass substrates in Ar gas had a strong orientation and that its surface form was comparatively smooth. The crystal structure of the thin films deposited on Si(100) and quartz glass substrate at temperatures of 700 and 800 °C by sputtering in a mixture of Ar and O₂ gases was the same as the crystal structure of LaCrO₃. The heating characteristics of a thin film heater on Si(100) substrate with Pt electrodes were evaluated by measurement of the equilibrium temperature‐current (T–I) and resistance‐equilibrium temperature (R–T) characteristics. The maximum equilibrium heating temperature was about 1100 °C. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 139(3): 18–25, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.1156