MOSFET开关过程的研究及米勒平台振荡的抑制

设计功率MOSFET驱动电路时需重点考虑寄生参数对电路的影响。米勒电容作为MOSFET器件的一项重要参数,在驱动电路的设计时需要重点关注。重点观察了MOSFET的开通和关断过程中栅极电压、漏源极电压和漏源极电流的变化过程,并分析了米勒电容、寄生电感等寄生参数对漏源极电压和漏源极电流的影响。分析了栅极电压在米勒平台附近产生振荡的原因,并提出了抑制措施,对功率MOSFET的驱动设计具有一定的指导意义。     

半桥结构中的SiC MOSFET串扰电压建模研究

SiC MOSFET凭借着低开关损耗、高工作频率与高工作温度点等优点,逐渐在高效率、高功率密度与高温的应用场合取代传统的硅功率器件。然而,在高速开关中带来的栅极串扰现象严重制约SiC器件的开关速度。传统的串扰抑制方法重点关注由栅极–漏极寄生电容引入的干扰电压,往往通过减小驱动回路阻抗的方式来降低串扰电压。该文基于SiC MOSFET器件的开关模态,提出考虑共源电感的分段线性化串扰电压模型。该模型基于器件数据手册及双脉冲实验提取的参数,考虑栅极–漏极电容、共源电感、体二极管反向恢复等非理想因素的影响。对比不同电压点、电流点与电阻值下实验与模型的输出结果。该模型表明,串扰电压是由器件栅极–漏极电容、共源电感与驱动回路阻抗共同作用的结果。单一降低驱动回路阻抗的方式对串扰电压的抑制效果有限。基于提出的模型,该文给出串扰电压抑制的指导方法,可直接用于SiC MOSFET驱动电路的设计。     

基于栅极驱动回路的SiC MOSFET开关行为调控

碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)与硅绝缘栅双极型晶体管相比,具有更低的开关损耗,更快的开关速度。但是,其高速开关过程对寄生参数非常敏感,容易激发高频振荡和过冲,给器件和电力电子装置的高效、安全运行带来不利影响。针对栅极驱动回路对器件开关行为的作用机理,基于电感钳位双脉冲测试电路,分析了SiC MOSFET开关过程的电路模型,并利用其数学模型分析了SiC MOSFET开关行为的典型特征,分析了不同栅极电阻、栅源电容、栅极驱动电压对开关行为的调控规律。分析发现,这些调控方法在抑制振荡和过冲的同时,会降低器件的响应速度,增加开关损耗。实验结果验证了模型与分析的正确性和有效性,可为SiC MOSFET的应用研究提供有益的支撑。     

带保护功能的功率MOSFET驱动电路

0 引言 通常功率场效管内部(栅-源极间)制作了一个保护用的齐纳二极管,由于该齐纳二极管的存在,也将使MOSFET管的栅极输入电容增大.因此,为了提高其开关速度,必须充分考虑栅极输入电容的影响,保证输入电容在开关过程中能很快充放电,因此,在设计功率MOSFET栅极驱动电路时,还必须使控制回路与功率MOSFET构成的主回路之间完全隔离.     

SiC MOSFET开关特性及多等级栅电压驱动电路

针对新型宽禁带功率半导体器件碳化硅(SiC)金属-氧化物半导体场效应晶体管(MOSFET),为了充分发挥其在高功率密度和高效率应用场合中的高速及低功耗特性,分析了SiC MOSFET的开关特性,提出了一种基于复杂可编程逻辑器件(CPLD)的新型多等级栅电压驱动电路(MGD)。在SiC MOSFET开关不同阶段,通过调整栅极驱动电压以改善其开关特性。与传统驱动电路(CGD)相比,提出的MGD在相同门极驱动电阻与栅源极电容前提下,能有效提高开关速度,降低电压电流尖峰、降低开关损耗。最后通过双脉冲实验,分析了栅极驱动电阻,栅源极电容对开关特性的影响,验证了MGD在改善开关特性方面具有明显的优越性。     

桥式电路中不同封装SiC MOSFET串扰问题分析及低栅极关断阻抗的驱动电路

由于SiC MOSFET开关速度较快,使得桥式电路中串扰问题更加严重,这样不仅限制了SiC MOSFET开关速度的提升,也会降低电力电子装置的可靠性。针对SiC MOSFET的非开尔文结构封装和开尔文结构封装的串扰问题分别进行分析,栅漏极结电容的充放电电流和共源寄生电感电压均会引起处于关断状态开关管的栅源极电压变化。提出一种用于抑制串扰问题的驱动电路,该驱动电路具有栅极关断阻抗低、结构简单、易于控制的特点。分析该驱动电路的工作原理,提供主要参数的计算方法。最后通过实验测试了两种结构封装SiC MOSFET的串扰问题,并且对提出的驱动电路进行了实验,验证了其正确性以及对串扰问题的抑制效果。     

利用附加电感实现高频功率MOSFET谐振栅极驱动

通过在功率MOSFET栅极驱动回路增加附加电感,利用栅极电容与附加电感的能量交换实现谐振栅极驱动,从而降低驱动功率损耗.保证该电路可以在高频情况下正常运行.实验验证了该方法的正确性与实用性.     

抑制SiC MOSFET桥臂串扰与栅源电压振荡的推挽式电容辅助电路分析及参数设计方法

碳化硅金属–氧化物半导体场效应晶体管(SiC metal-oxide-semiconductor field-effect transistor, SiC MOSFET)在高速开关中引起的桥臂串扰和栅极电压振荡严重制约了其开关速度。针对已提出的基于推挽式电容辅助电路(push-pull-capacitor auxiliary circuit, PPCAC)的SiC MOSFET驱动工作过程进行了进一步的分析。结合分析，将SiC MOSFET桥臂串扰以及漏源电压振荡引起的栅源电压振荡2个问题归一化，通过推挽电容充放电时刻以及桥臂串扰约束，提出了一种推挽电容参数设计方法。通过该设计方法，可使得PPCAC在抑制SiC MOSFET桥臂串扰与栅源电压振荡的基础上，改善其开通关断速度。实验结果验证了所提出设计的有效性。     

并联碳化硅MOSFET短路振荡机理

碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)为高性能电力电子技术提供了技术保障,其短路承受能力是进一步提升电力电子变换器可靠性的关键;特别是在大功率场合,经常将SiC MOSFET并联使用,然而影响并联SiC器件短路振荡的关键因素并不十分明确,振荡机理有待进一步研究。此处以并联SiC MOSFET为研究对象,建立在短路工况下的等效数学模型,分析影响并联短路特性的关键因素并进行实验验证,归纳短路振荡机理。理论分析与实验结果表明,当并联SiC MOSFET发生短路故障时,栅极驱动电阻和功率回路杂散电感是导致器件并联系统振荡的主要因素,过小的栅极驱动电阻使得并联系统振荡频率和尖峰增大;过大的功率回路杂散电感导致系统振荡频率降低,而振荡尖峰增大,系统的剧烈振荡不利于SiC MOSFET稳定性提高。     

基于干扰动态响应机理的SiC MOSFET驱动设计

目前碳化硅(SiC)MOSFET大多沿用Si MOSFET和IGBT的驱动设计方法.然而,由于SiC MOSFET相比Si器件具有更高的开关速度,因而栅极内阻、驱动回路电感和功率回路电感导致的栅源电压干扰情况也值得探索.该文分析栅源电压干扰产生的过程,进而归纳提炼出一种基于干扰动态响应机理的SiC MOSFET驱动参数标幺化设计方法.从开关结电容的等效电路出发,推导出功率回路和驱动回路的传递函数,基于驱动和功率双回路传递函数,研究揭示栅源电压的干扰动态响应机理.进而,引入标幺化的参数表达形式,以标准量化驱动参数对于栅源电压干扰传导路径的影响,提出基于干扰动态响应机理的SiC MOSFET驱动设计原则.最后,搭建双脉冲实验平台,验证该驱动设计原则的合理性.     

AC/DC变换器传导EMI实验分析

开关电源传导EMI问题一直都备受关注,目前国内外的研究主要还是定性研究,而定量的分析可以更加准确细致的找出传导EMI形成的机理。针对两种典型工作状态下的AC/DC变换器,测试得到了其传导EMI的频域波形,MOSFET漏极与源极间电压波形以及提取了电路中的主要寄生参数,通过对比与定量的分析计算,找出了其传导EMI几处重要峰值形成的原因。最后得出了变压器原边与副边漏感、MOSFET源极与漏极间寄生电容以及MOSFET与散热片之间的寄生电容,是影响开关电源的传导EMI的重要因素。在开关器件导通或者关断时,开关电源的工作状态发生改变,此时漏感或者器件的寄生电容中的剩余能量会引起高频振荡,进而引起了传导EMI尖峰。     

Hybrid MOSFET/driver for ultra-fast switching

The ultra-fast switching of power MOSFETs, in about 1 ns, is very challenging. This is largely due to the parasitic inductance that is intrinsic to commercial packages used for both MOSFETs and drivers. Parasitic gate and source inductance not only limit the voltage rise time on the MOSFET internal gate structure but can also cause the gate voltage to oscillate. This paper describes a hybrid approach that substantially reduces the parasitic inductance between the driver and MOSFET gate, as well as between the MOSFET source and its external connection. A flip-chip assembly is used to directly attach a die-form power MOSFET and driver on a PCB. The parasitic inductances are significantly reduced by eliminating bond wires and minimizing lead length. The experimental results demonstrate ultra-fast switching of the power MOSFET with excellent control of the gate-source voltage.     

一种改进型抑制SiC MOSFET桥臂串扰的门极驱动设计

由于传统驱动中SiC MOSFET在高开关频率的情况下其寄生参数造成的桥臂串扰更加严重,而现有的抑制串扰驱动电路大多是以增加开关损耗,增长开关延时和增加控制复杂度为代价抑制串扰。因此,根据降低串扰产生过程中驱动回路阻抗的思想,提出一种在栅源极间增加PNP三极管串联二极管和电容的新型有源密勒钳位门极驱动设计,并分析其工作原理,对改进驱动电路并联电容参数进行计算设计。最后,搭建了直流母线电压为300V的同步Buck变换器双脉冲测试实验平台,分别与传统串扰抑制电路,典型串扰抑制电路的正负向串扰电压尖峰抑制效果和开通关断速度做对比分析。实验结果表明,提出的串扰抑制驱动电路正负向电压尖峰分别比传统和典型串扰抑制电路降低了80%和40%,同时减少了32%的器件开关延时。     

Investigation of false triggering mechanism

This paper discusses a problem that a half‐bridge circuit can generate, namely a false trigger by high‐speed switching transition. In general, a false trigger occurs by charging a gate–source capacitance because of high‐speed voltage transition and influx of current via a reverse transfer capacitance. Therefore, it is thought that the ratio of the input capacitance and the reverse transfer capacitance is important to check whether a false trigger occurs. However, we find another reason and propose a novel assumption. A novel false triggering mechanism appears by considering the source‐side parasitic inductance. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 2-MHz 2-kW voltage-source inverter for low-temperature plasmagenerators: implementation of fast switching with a third-order resonantcircuit

This paper presents a specially designed third-order resonant circuit intended to achieve fast switching operation for a voltage-source series-resonant inverter using four MOSFETs. The third-order resonant current superimposed on a sinusoidal load current helps to quickly charge or discharge the output capacitance of each MOSFET. This results not only in a reduction of the commutation period which is required to turn the MOSFET on and off, but also in an improvement of the displacement factor at the output of the inverter. Moreover, the third-order resonant circuit acts as a low-pass filter to suppress the parasitic oscillation between line inductance and stray capacitance. The viability and effectiveness of the third-order resonant circuit is verified by a 2 MHz 2 kW prototype inverter developed for a low-temperature plasma generator     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

一种电流型D类功放高频自激驱动电路

为了解决物理美容设备中电流型D类功放自激驱动栅源电压过高的问题,设计了一种实用电流型D类功放的高频自激驱动电路。通过改变电路中直流偏置电压、MOS管驱动级的电容、漏源间的电容以及两管漏极间电容、供电电压的方法,解决驱动栅源电压过高的问题。通过理论和试验分析,完成电路的设计。通过试验,做到了栅源电压不超过±30V,谐振频率可以达到2MHz左右。该电路具有分离元件少,结构简单,效率高等优点。将该电路实际应用到一款物理美容设备中时,达到了很好的消脂、美白、嫩肤效果。     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

1200V碳化硅MOSFET与硅IGBT器件特性对比性研究

搭建了输出特性测试电路、漏电流测试电路、双脉冲测试电路和Buck电路,对1 200 V SiC MOSFET和Si IGBT的输出特性、漏电流、开关特性和器件损耗进行了对比研究,分析了SiC MOSFET的主要优缺点。分析结果表明,SiC MOSFET在高温条件下依然拥有稳定的阻断能力;在同样的工作条件下,SiC MOSFET损耗更小,适合在高频率、大功率场合下使用;SiC MOSFET的跨导低,导通电阻大,所以门极驱动电压需要比较大的摆幅(-5/+20 V);由于开关速度很快,SiC MOSFET对线路杂散参数更加敏感。