Schwarz lemma for driving point impedance functions and its circuit applications

In this paper, a boundary version of the Schwarz lemma is investigated for driving point impedance functions and its circuit applications. It is known that driving point impedance function, Z(s) = 1 + c_p(s − 1)^p + c_{p + 1}(s − 1)^{p + 1} + ..., p > 1, is an analytic function defined on the right half of the s-plane. Two theorems are presented using the modulus of the derivative of driving point impedance function, |Z′(0)|, by assuming the Z(s) function is also analytic at the boundary point s = 0 on the imaginary axis with . In the obtained inequalities, the value of the function at s = 1 and the derivatives with different orders have been used. Finally, the sharpness of the inequalities obtained in the presented theorems is proved. Simple LC circuits are obtained using the obtained driving point impedance functions.     

A method for rejecting 3k-th harmonics in bandpass 6N-path filters

In this paper, a method for 3 -th ( ) harmonics rejection in 6 -path filters is proposed, and the related analysis is provided. Using a single-ended-input to differential-output structure, the filter selectivity around even harmonics are also suppressed. Accordingly, a proof-of-concept band-pass filter is designed, and postlayout simulations in the 90-nm CMOS technology are carried out, which covers an input frequency range from 200 MHz to 1.2 GHz with a channel bandwidth of 10 to 15.5 MHz. The achieved third harmonic rejection at 1-GHz local oscillator (LO) frequency is about 43 dB. Over the entire radio frequency (RF) range, the in-band IIP3 and noise figure are better than 1.5 dBm and 5.3 dB, respectively. The power consumption of the analog circuitry is 21 mW from the 1.2-V supply, whereas the digital clock generation circuitry consumes between 0.9 and 5.2 mW, depending on the center frequency of the filter.     

FPGA-based system for effective IQ imbalance mitigation of RF power amplifiers

To provide an adequate signal integrity to a power amplifier (PA), we propose a digital system for the degradation at the transmitter path, and it is implemented on a field-programmable gate array (FPGA) board. The proposed system offers the following features: A -ary quadrature amplitude modulation (QAM) digital signal generation and in-phase/quadrature (IQ) imbalance mitigation, and by default, it performs as a predistortion model extraction from PA-measured data. The simulations and tests provided are performed to effectively verify the PA linearity by using 256-QAM signals. The nonlinearities are predicted as a reliable solution for linearizing the PA from measurements of AM/AM and AM/PM conversion curves. The performance is evaluated in terms of linearity, computation complexity, and FPGA hardware synthesis according to a dependability compliance of digital signal processing. Finally, the model is validated with input/output data observations to linearize the model with a fitting normalized mean squared error (NMSE) of around  dB, a spurious free dynamic range of 40 dBm, and an adjacent channel power ratio reduction by  dBm, for a class-AB broadband radio frequency PA GaN HEMT of 10 W working at 2.34 GHz.     

Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms

Many of the modern deep learning, machine learning, and artificial intelligence algorithms use adders, multipliers, and multiply-accumulators (MACs) with mixed precisions. In general, fixed-point and floating-point adders, multipliers, and MACs are used in mixed-precision hardware, such that the above algorithm can choose appropriate hardware for its processing. This paper proposes an efficient mixed-precision MAC circuit that can perform fixed-point and floating-point operations. The proposed design uses Han-Carlson adder with late carry or end-around carry in its accumulator design; as a result, delay and energy of the circuit reduce by and respectively, when compared with the existing designs from the literature.     

2‐matrix‐based finite element linear solver for fast transient thermal analysis of high‐performance ICs

In this article, we propose ²‐based finite element (FE) solver for transient thermal analysis of high‐performance integrated circuits (ICs). ²‐matrix is a special subclass of hierarchical matrix or ‐matrix, which was shown to provide a data‐sparse way to approximate the matrices and their inverses with almost linear space and time complexities. In this work, we show that ²‐based mathematical framework can also be applied to FE‐based transient analysis of thermal parabolic partial differential equations. We show how the thermal matrix can be approximated by ²‐representations with controlled error. Then, we demonstrate that both storage and time complexities of the new solver are bounded by , where N is the matrix size. The method can be applied to any thermal structures for both steady and transient analysis. The numerical results from 3D ICs demonstrate the linear scalability of the proposed method in terms of both memory footprint and CPU time. The comparison with existing product‐quality LU solvers, CSPARSE and UMFPACK, on a number of 3D IC thermal matrices, shows that the new method is much more memory efficient than these methods, which however prevents the demonstration of the potential speedup of the proposed method over those methods. Copyright © 2014 John Wiley & Sons, Ltd.     

Performance improvement of DC-DC converter using L-D-based modified GaN-FET driver

Bootstrap capacitor in FET gate driver plays an important role in the transient performance of the half bridge configured synchronous buck DC-DC converter especially in the top switch. In this paper, a new bootstrap capacitor based GaN-FET driver is proposed. This new GaN-FET driver is tested in a synchronous buck converter for performance verification like immunity, transient response, and voltage ringing. A comparison study with the existing LM5113 (Texas Instrument)–based driver for GaN-FET and IR2110-based Si-MOSFET driver on a DC-DC converter is carried out to show the performance improvement using the proposed GaN-FET driver. The simulation study is performed on spice-based NI-Multisim 14.1. Finally, the designed GaN-FET driver is tested on a 60-W synchronous buck DC-DC converter in open-loop and closed-loop configuration.     

Analysis,design, and minimum phase selection of high power interleaved DC–DC converter

The primary use of interleaved bidirectional DC–DC converters (IBC) is for high current applications due to the inherent property of ripple cancellation, high redundancy, and improved efficiency. Proper analysis and design are required to improve the power density and reduce the cost of the $N$-phase IBC. Ripple current analysis plays a vital role in choosing the inductor and filter capacitors to minimize the size of an IBC. This paper presents the simple and generalized formulas for the current ripple minimization of $N$-phase IBC. Also, the inductor is designed with two different core materials, namely, Ferrite and Sendust. It is observed that the area product and weight of the magnetics have been reduced by 22% and 23%, respectively, for Sendust core in comparison with the Ferrite core. Furthermore, a discussion regarding the thermal analysis of IGBT modules to select an appropriate heat sink is stated. Moreover, the minimum phase selection has been proposed by considering several constraints such as area product of the core, discrete components size based on ripple analysis, cost of all components, and converter efficiency. The prototype of the selected minimum phase IBC has been developed and tested for a 7.5 kW power level using TMS320F28335.     

Design of a low‐power high open‐loop gain operational amplifier for capacitively‐coupled instrumentation amplifiers

We present the design of a low‐power high open‐loop gain opamp for use in chopper‐stabilized capacitively coupled instrumentation amplifiers (CCIAs). The opamp utilizes the current‐reuse folded‐cascode topology and a low‐power gain‐boosting technique to maximize its power efficiency and open‐loop gain. The proposed technique is applied to the designs of two CCIAs: the conservative CCIA with a moderate current scaling ratio and the stringent CCIA with a very high current scaling ratio. Utilizing the current scaling ratio of 4:1, the conservative CCIA, designed and fabricated in a 0.18 μ m CMOS process, consumes a total current of 1.69 μ A from a 0.8‐V supply voltage and achieves a thermal noise floor of 56.5 nV/ . Utilizing the current scaling ratio of 38:1, the stringent CCIA, designed and simulated in a 0.13 μ m CMOS process, consumes a total current of 1.4 μ A and achieves a thermal noise floor of 48 nV/ . The proposed design technique should benefit the designs of low‐power instrumentation amplifiers in advanced processes in which channel‐length modulation and the limited current consumption and supply voltage make the designs of high open‐loop gain opamps difficult. Copyright © 2017 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

Single switch quadratic boost converter with continuous input current for high voltage applications

In this paper, a novel non-isolated very high step-up DC-DC converter is presented. The introduced converter benefits from various advantages, namely, very high voltage gain, low voltage stress on the active switch, and continuous input current with low ripple. Therefore, the presented converter is suitable for renewable energy applications. In addition, the energy of the leakage inductance of the coupled inductor is successfully recovered, and the voltage spike of the active switch is clamped during the turn-off process. Hence, a switch with low can be used, which decreases the conduction losses as well as cost of the converter. Furthermore, the voltage stress of the output diode is decreased, which reduces the reverse recovery problem. The steady-state analysis and design considerations of the proposed converter are discussed. Finally, the theoretical analysis is validated with the experimental results at an output power of 150 W.     

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs.     

A new method to realize nonrational driving-point functions

This paper presents a new synthesis procedure for nonrational driving-point functions by defining and using the operator. The operator is defined, and its properties are explored. Applying the Stieltjes transform on the operator, the Padé approximant or the continued fraction form of the nonrational network function can be achieved with reduced computational complexity. Thus, the classical Foster and Cauer form or other techniques may be applied to synthesize network functions. The application of this work is demonstrated by considering certain functions such as the square root, inverse tangent, logarithm, and Lambert's W function. A set of conditions called synthesis criteria is proposed, which should be satisfied by a nonrational function to be realizable.     

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

This study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.     

Process-induced variability modeling of subthreshold leakage power considering device stacking

The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFET into nanometer regime, and has become a significant component of total IC power dissipation. The issue is further aggravated with the inability to gauge the tolerance of process parameters around their nominal value. Consequently, the drive to improve the static power prediction has enticed accurate and reliable modeling of leakage current, specifically for ultralow power applications. In contrast to gate- and band-to-band-tunneling leakages, subthreshold leakage exhibits high susceptibility to process variations and hence has been considered for variability modeling. Fluctuations in the device electrical and geometry parameters result in a wider distribution of subthreshold leakage current. Hence, taking into account stacking effect, an analytical variability model to estimate subthreshold leakage power in subthreshold circuits, in the presence of threshold voltage variations is proposed. Further, the impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model-generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700 computationally faster than SPICE simulations with mean error being less than 0.19%.     

Constant switching frequency-based delta-sigma modulation of single-phase AC–AC zeta converter

Direct pulse width modulated (PWM) AC–AC converters, derived from their DC–DC counterparts, serve as promising media for AC–AC power conversion because they offer benefits, such as single-stage power conversion, absence of bulky DC links, and small footprint. In this study, a single-phase ( $1-\varphi$) AC–AC zeta converter was analyzed under buck, boost, and buck-boost operations. Delta-sigma modulation (DSM) technique, known for its simple logic implementation, excellent reference-tracking property, robust control, and fast transient response, was employed for the load voltage control of a $1-\varphi$ AC–AC zeta converter. However, the conventional DSM technique relies on a fixed hysteresis band (FHB) for restricting the integrated (sigma) error (delta) between the reference and estimated control voltages within a narrow band, which causes the converter to operate at a variable switching frequency (VSF). Although VSF enhances the converter performance with low total harmonic distortion (THD) and high degree of flexibility over waveform quality, it poses serious implications such as higher switching losses, putting more strain on thermal management of switches. This paper presents a constant switching frequency-based DSM technique based on an adaptive hysteresis band (AHB) for a $1-\varphi$ AC–AC zeta converter. The converter is controlled using FHB-DSM and AHB-DSM techniques, and a comparison is drawn between the two in terms of various performance indices. In this comparison, FHB-DSM serves as a benchmark and an optimum switching frequency based on AHB-DSM technique is determined, which exhibits low switching losses while maintaining the same THD limits, dynamic response, and waveform quality as that of FHB-DSM technique. The proposed strategy was validated by simulation studies in MATLAB/SIMULINK software. Furthermore, a real-time simulator, OPAL-RT (OP4510), was used to validate the study with real-time implementation.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Ultra‐low‐noise large‐bandwidth transimpedance amplifier

Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low‐noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt‐shunt configuration, the equivalent input noise decreases as the feedback resistor (R_F), which also sets the gain, increases. Unfortunately, as R_F increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of R_F and reduces as R_F increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large‐bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/ , corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.     

Efficient hardware implementations of point multiplication for binary Edwards curves

This paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5 M + 4 S + 2 D and 5 M + 4 S + 1 D , respectively, where, M , S , and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works.     

Hybrid-triggered fault detection filter design for networked Takagi–Sugeno fuzzy systems subject to persistent heavy noise disturbance

In the network environment, the single time-triggered scheme wastes limited bandwidth resources due to all the sampled data are transmitted to the networks, and the single event-triggered scheme may increase system error because of ignoring factors such as changes in network utilization. To reduce the design conservatism, this paper is concerned with the hybrid-triggered L₁ fault detection filter design for a class of nonlinear networked control systems (NCSs) described by Takagi–Sugeno (T-S) fuzzy model. Taking the effects of time-triggered scheme and event-triggered scheme into consideration simultaneously, we construct a fuzzy fault detection system. New results on stability and L₁ performance are proposed for fuzzy fault detection system by exploiting the Lyapunov–Krasovskii functional and by means of the integral inequality method. Specially, attention is focused on the design of fault detection filter that guarantees a prescribed L₁ noise attenuation level . Finally, two examples are presented to demonstrate the effectiveness of the proposed method.