3D Electrostatics of Carbon Nanotube Field-Effect Transistors

The three dimensional (3D) electrostatics of carbon nanotube field-effect transistors (CNTFETs) is studied by solving the Poisson equation self consistently with equilibrium carrier statistics of CNTFETs. The 3D Poisson equation is solved using the method of moments. We examine how the 3D environment affects the electrostatics of a 30 nm intrinsic CNT under equilibrium conditions. We show that for a CNTFET with a planar gate, the scaling length (the distance by which the source and drain fields penetrate into the channel) is mostly determined by the gate oxide thickness. The contact geometry can also play an important role on the scaling length. A smaller contact results in shorter scaling length and better gate control. We finally show that the top gated geometry offers obvious advantage over the bottom gated geometry in terms of gate electrostatic control.     

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.     

Electrical characterization and parameter extraction of organic thin film transistors using two dimensional numerical simulations

In this paper a performance based comparison of top and bottom contact organic thin film transistor (OTFT) device structures, using two dimensional numerical simulations has been carried out. In addition to this, investigations pertaining to the estimation of contact resistance in these OTFTs were also performed. To estimate contact resistance the conventional transmission line method and modified transmission line method (M-TLM) were respectively invoked. Our simulation results clearly indicate that the latter is more accurate in the estimation of contact resistance compared to the conventional method. Furthermore, the M-TLM was used to estimate the gate voltage and film thickness dependence of the contact resistance for the two device structures. The observed results have been explained on the basis of the significantly lowered area of carrier injection and extraction regions, at the source/channel and channel/drain interface respectively, in bottom contact transistor that lead to its inferior performance over the top contact transistor.     

NMOSFET ESD self-protection strategy and underlying failuremechanism in advanced 0.13-μm CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L_npn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I_t2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device     

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling.     

Performance optimization of MOS-like carbon nanotube-FETs based on electrostatic doping

Due to carriers Band-To-Band-Tunneling (BTBT) through channel-source/drain contacts, Conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed. The Non-Equilibrium Green’s Function (NEGF) formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold performance, which are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends highly on the choice of tuning voltage value, which should be paid with much attention to obtain a proper trade-off between power and speed in application.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Monte Carlo simulation of nanoelectronic devices

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.     

Temperature-dependent short-channel parameters of FinFETs

The remarkable development and continual proliferation of research in the nanotechnology field have led to improvement in the efficiency of elementary devices. To improve their performance, the parameters of such devices can be scaled down while optimizing their characteristics. However, this simultaneously results in degraded switching characteristics and the appearance of short-channel effects. Multigate-based fin-shaped field-effect transistors (FinFETs) represent a new option to address all these problems. However, thermal failure of FinFET devices under nominal operating conditions is an important issue in the design and implementation of high-speed semiconductor devices. It is also seen that bulk FinFETs exhibit better thermal performance compared with silicon-on-insulator FinFETs. In the work presented herein, various FinFET characteristics including the subthreshold swing, drain-induced barrier lowering, threshold voltage, and drain current were investigated as functions of temperature. The (effective) channel length is larger than the physical gate length (in off-state) due to the undoped underlap regions. This paper also discusses the effects of drain, source, and gate overlap.     

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.