Electrical properties of ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructures

Ultrathin HfO₂ gate dielectrics have been deposited on strained Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. The polycrystalline HfO₂ film with a physical thickness of ∼6.5 nm and an amorphous interfacial layer with a physical thickness of ∼2.5 nm have been observed by high resolution transmission electron microscopy (HRTEM). The electrical properties have been studied using metal-oxide-semiconductor (MOS) structures. The fabricated MOS capacitors on Si_0.69 Ge_0.3C_0.01 show an equivalent oxide thickness (EOT) of 2.9 nm, with a low leakage current density of ∼4.5 × 10 ^{− 7} A/cm² at a gate voltage of –1.0 V. The fixed oxide charge and interface state densities are calculated to be 1.9 × 10¹² cm^{− 2} and 3.3 × 10 ¹¹ cm^{− 2}eV⁻¹, respectively. The temperature dependent gate leakage characteristics has been studied to establish the current transport mechanism in high-k HfO₂ gate dielectric to be Poole–Frenkel one. An improvement in electrical properties of HfO₂ gate dielectrics has been observed after post deposition annealing in O₂ and N₂ environments.     

Single-grained PZT thin films for high level FRAM integration—fabrication and characterization

Abstract

A new method for formation of large single grains as large as 40 μm in length of the sputter-deposited PZT(65/35) thin films has been developed in this research group. Crystallized PZT dots were used as a seed and the grains were laterally grown to form a square pattern on the Pt substrate. It turned out that the electrical characteristics of the single grained PZT thin films were much superior to those of the poly-grained PZT thin films. The leakage current was measured to be less than 8x10^?8 A/cm², the breakdown field more than 1,240 kV/cm, the value of saturation polarization and remanent polarization as high as 42 μC/cm², 30 μC/cm², respectively. No degradation of the polarization properties was observed even after the 2×10¹¹ cycles at 1 MHz using a ± 10 V wave form in Pt/PZT/Pt structure. The accelerated retention test revealed that it takes more than 6×10⁷ years for the remanent polarization to be reduced down to 80% of the original value.     

Low temperature preparation of ferroelectric SrBi2Ta2O9 thin films by a modified RF magnetron sputtering technique

Abstract

Bi–layered ferroelectric SrBi₂Ta₂O₉ (SBT) films were successfully prepared on Pt/Ti/SiO₂/Si substrates at 650°C by a modified rf magnetron sputtering technique. The SBT films annealed for 1 h in O₂ (760 torr) and again for 30 min in O₂ (5 torr) at 650°C show a average grain size of about 49 nm. The SBT films annealed at 65 0°C have a remanent polarization (P_r) of 6.0 μC/cm² and coercive field (E_c) of 36 kV/cm at an excitation voltage of 5 V. The films showed fatigue–free characteristics up to 4.0 × 10¹⁰ switching cycles under 5 V bipolar pulse. The retention characteristics of SBT films looked very promosing up to 1.0 × 10⁵ s.     

LEAKAGE CURRENT CHARACTERISTICS OF Pt/Ba0.6Sr0.4TiO3/Pt THIN-FILM CAPACITORS

ABSTRACT

Leakage current characteristics of Pt/Ba_0.6Sr_0.4TiO₃/Pt ferroelectric thin-film capacitors were investigated at the temperature range from 273 K to 393 K. It is implied that there are two conduction regions in the capacitors, i.e. ohmic behavior at low voltage (< 0.4 V) and Poole-Frenkel or Schottky emission mechanism at high voltage (> 1.8 V). The depletion layer widths calculated from Poole-Frenkel model and Schottky emission model are 36.9 nm～ 61.5 nm and 6.8 nm～ 11.5 nm, respectively. Moreover, the trapped level, the Schottky barrier height, the constant and the effective Richardson constant are 0.56 V, 0.49 V, 0.227A/cm² · V and 1.15 × 10^?7 A/cm² · K², respectively.     

CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT

In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O₂. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O₂, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10^{? 5} A/cm² at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr_0.8Bi_2.2Ta₂O₉ (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.     

Ferroelectric properties of plzt thin films prepared by mocvd

Abstract

Lanthanum-modified lead zirconate titanate (PLZT) thin films have been grown on Pt/SiO₂/Si substrate at 650[ddot]C by metalorganic chemical vapor deposition. The relative dielectric constant increased as the La content was increased up to about 5 atomic percent (at%). The remanent polarization and coercive field decreased from 30 to 20 μC/cm² and from 53 to 30 kV/cm, respectively, with increasing La content in the range of 0–13 at%. The leakage current of PLZT film was 3 × 10^?9 A/cm² at an applied voltage of 3 V. The degradation of switched charge density of PLZT film was not observed even at 2 × 10¹¹ cycles.     

Numerical simulation on novel FinFETs: asymmetric poly-silicon gate FinFETs and TiN gate FinFETs

We report our numerical study on the device performance of an asymmetric poly-silicon gate FinFET and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-silicon FinFET structure and TiN gate FinFET structures exhibit superior V _T tolerance over the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V _T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation further revealed that the threshold voltage (V _T) can be controlled within the range of −0.1∼+0.5 V through varying the doping concentration of the asymmetric poly-silicon gate region from 1.0×10¹⁸ to 1.0×10²⁰ cm⁻³.     

Influence of ion beam bombardment on characteristic of InGaN/GaN single quantum well grown by metal–organic chemical vapor deposition

The influence of ion beam bombardment on sapphire substrate was investigated on the electrical and optical characteristics of Indium–Gallium–Nitride/Gallium–Nitride (InGaN/GaN) single quantum well (SQW) structure. Ion bombardment of N⁺, He⁺, H⁺ ions were made on single crystal substrate of sapphire with dose of 1?×?10^14–17 ions/cm². The InGaN/GaN SQW was fabricated on the ion beam bombarded sapphire substrate in two-flow Metal Organic Chemical Vapor Deposition (MOCVD) equipment. The thickness of InGaN/GaN SQW was about 20 nm and the composition of InGaN/GaN SQW was found to be In_0.1Ga_0.9N. In PL spectra, it is found that InGaN/GaN SQW was emitted from 441.1 to 446.6 nm (2.8–2.7 eV). The highest mobility value of 118 cm²/V–S and the lowest carrier concentration of 3.41?×?10¹⁷/cm² was found for N of 10¹⁶ ions/cm² ion beam bombarded sample. The optimal condition for InGaN/GaN SQW on sapphire substrate of ion beam bombardment was deduced to be N⁺ ion dose of 10¹⁶ ions/cm².     

Performance enhancement of recessed silicon channel double gate junctionless field-effect-transistor using TCAD tool

In this paper, we propose an n-type double gate junctionless field-effect-transistor using recessed silicon channel. The recessed silicon channel reduces the channel thickness between the underlap regions, results in lowering the number of charge carriers in the silicon channel, and therefore, diminishing the OFF-current in the device. The proposed device shows similar electrical characteristics with improved transconductance, as compared to the conventional double gate junctionless field-effect-transistor. The effect of channel length scaling on the performance have been investigated, and it has been found that the recessed junctionless device shows higher ON-to-OFF current ratio, lower subthreshold swing and better immunity against the short channel effects, namely threshold voltage roll-off and drain-induced-barrier-lowering. For a channel length of 20 nm the OFF-current of the order of 1.20?×?10^–14 A/µm, ON-to-OFF current ratio of the order of 6.01?×?10¹⁰, subthreshold swing of the value of 67 mV/dec, and DIBL of 37.8 mV V^?1 has been achieved with the proposed junctionless device, in comparison of conventional double gate junctionless FET. The performance of proposed device with respect to the variations in depth and length of recessed silicon area, has also been presented as a roadmap for further tuning of its electrical behaviour. Comparatively, steeper DC transfer characteristics and improved rail-to-rail swing in transient behaviour has been reported with the designed complementary metal–oxide–semiconductor inverter, based on recessed double gate junctionless FET. The proposed recessed silicon channel double gate junctionless field-effect-transistor has been simulated using TCAD tool.

     

Effect of discharge power density on the properties of Al and F co-doped ZnO thin films prepared at room temperature

ZnO transparent conducting thin films co-doped with aluminium and fluorine (AZO:F) were prepared on glass substrates by RF magnetron sputtering at room temperature. The effect of discharge power density on the microstructure, surface morphology, electrical and optical properties was investigated. From XRD analysis, it was revealed that the intensity of (002) favoured orientation of ZnO films increased with power density from 2.6 to 6.1?W/cm² and then turned to a randomly orientated structure as power density continuously increased to 7.8?W/cm². The film prepared at 6.1?W/cm² showed a better crystallization and microstructure with larger, pyramid-like grains that were approximately 180?nm long and 90?nm wide. As a result, the electrical resistivity of the AZO:F films had a minimum of 4.1?×?10^?4???cm. The improvement in the electrical resistivity of AZO:F films was due to the increase in carrier concentration from 8.8?×?10²⁰ to 1.38?×?10²¹?cm^?3 and the mobility from 5.8 to 11.8?cm² V^?1 s^?1. The increase in carrier concentration with power density was also found to affect the optical property of the films due to the Moss-Burstein shift.