PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract

The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO₂ buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity of the semiconductor was the same as that expected for ferroelectric switching.     

Recent progress of FET-type ferroelectric memories

Abstract

Recent progress of FET-type ferroelectric memories is reviewed. It is described that insersion of a buffer layer between the ferroelectric film and Si substrate is essential in preventing interdiffusion of the constituent elements. It is also shown, however, that existence of the buffer layer degrades the data retention characteristic severely. Necessary conditions to solve the short retention time problem are discussed, paying particular attention to comparison of MFIS (metal-ferroelectric-insulator-semiconductor) and MFMIS structures. Finally, a novel ferroelectric-gate FET is proposed, in which the depolarization field is expected not to be generated in the ferroelectric film.     

Electrical characteristics of Pt-SBT-Polysilicon (MFIP) capacitors with yttrium oxide as the buffer layer

Abstract

MFIS structures with Strontium Bismuth Tantalate (SBT) as the ferroelectric thin film and yttrium oxide as the buffer layer have been fabricated on polysilicon layer as well single crystal silicon. Yttrium oxide film was deposited by electron beam evaporation and SBT was deposited by spin on MOD technique. Preliminary analysis of capacitance vs voltage (C-V) curve shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. For an applied DC bias of ± 5 V, the C-V curve shows a memory window of ± 2 V.     

Characteristics of ferroelectric gate mos and mosfets

Abstract

Electrical characteristics of metal-insulator-semiconductor (MIS) capacitors of a variety of ferroelectric materials like lead zirconate titanate (PZT), lead titanate (PT) and barium magnesium fluoride (BMF) on p-silicon have been studied. PZT was deposited by r.f. magnetron sputtering from a composite target and PT from co-evaporation. The films were annealed in oxygen atmosphere in the temperature range 550–700°C for various times. PZT and PT films which are directly deposited on silicon showed low effective dielectric constant.¹⁰ For normal applied bias voltages (±5 V), the C-V curves did not show significant hysteresis. The effective dielectric constant was improved significantly by the incorporation of a buffer layer. BMF film was deposited in ultra high vacuum on a heated substrate and the film was encapsulated by a zirconium oxide layer. The C-V curves for these MIS capacitors shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization.     

Improvement of Dielectric and Interface Properties of CeO2 Buffer Layer by Using the Metal Seed Layer and N2 Plasma Treatment

In this paper, we investigated the feasibility of cerium oxide (CeO₂) films as buffers layer of MFIS (metal ferroelectric insulator semiconductor) type capacitors. CeO₂ layer were prepared by a two-step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By applying a cerium (Ce) metal seed layer of 4 nm, unwanted SiO₂ layer generation was successfully suppressed at the interface between the buffer layer and the Si substrate. After N₂ plasma treatment, the leakage current was reduced by about 2-orders. By employing a N₂ plasma treatment, we were able to successfully obtain good properties at the interface between the buffer layer and the Si substrate.     

MOCVD of Pb(Zr x Ti1-x )O3 thin films on MgTiO3/Si substrates and their electrical properties

Abstract

Pb(Zh _x , Ti_1-x )O₃(PZT) thin films were deposited on Si substrates using MgTiO₃ as the buffer layer and the electrical properties of those MFIS structures were investigated. PZT and MgTiO₃ films were made by MOCVD using ultrasonic spraying technique. Perovskite PZT films have been succesfully made at the substrate temperature of 550 to 600°C only when using MgTiO₃ buffer layer. AES depth profile analysis and RBS analysis revealed that there is no remarkable interdiffusion and no formation of reaction layer between PZT and MgTiO₃ and/or between MgTiO₃ and Si substrate. The capacitance-voltage (C-V) curves of the MFIS structure which were made with PZT and MgTiO₃buffer layer have shown the hysteresis resulted from the ferroelectric switching of the PZT films.     

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

Abstract

We have investigated the roles of buffer layer in the Pt/SBT-Y₂O₃/p-Si (MFIS) capacitors. We found that the insertion of Y₂O₃ buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×10¹²/cm² were generated due to the additional process step for Y₂O₃ deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y₂O₃ buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.     

Dielectric Characteristics of In-Plane Polarized Lead Zirconate Titanate Thin Films on Oxide Layers

Sol-gel derived lead zirconate titanate (PZT) films have been prepared on STO-passivated silicon substrates. The STO buffer layer of thickness about 55 nm is prepared by rf-magnetron sputtering. XRD results reveal that the PZT film has well-crystallized perovskite phase, indicating that the thin STO layer can effectively prevent reaction and inter-diffusion between the PZT film and silicon substrate. Interdigitated electrodes (IDEs) have then been deposited on the PZT film by magnetron sputtering and patterned using the standard photolithography. With the IDEs, the dielectric and ferroelectric properties of the PZT film under transverse or in-plane electric fields have been investigated. By assuming a uniform distribution of electric field (in-plane electric field model), the estimated relative permittivity of the PZT film is about 2100, while the dielectric loss is less than 1%. Good in-plane polarization hysteresis loop is observed, showing an observed remanent polarization value of 21 μC/cm², which is comparable to that of a PZT film with both top and bottom electrodes. The in-plane polarized PZT/STO/SiO₂/Si film can be used to fabricate d₃₃-mode unimorph bending transducers, which will have much better performance than the conventional bending transducers driven electromechanically through the piezoelectric d₃₁ mode.     

Application of fluorinated SiO2 interlayer dielectrics for ferroelectric memory

Abstract

Fluorine-doped silicon oxide (SiOF) as interlayer dielectric (ILD) was deposited over PZT capacitors by electron cyclotron resonance (ECR) chemical vapor deposition using SiF₄ and N₂O gases. In the conventional deposition of SiO₂ ILD layer using hydrogen-contained source gases, the properties of ferroelectric capacitors are known to be degraded during the formation of SiO₂ layer. In this study, we examined the degradation of electrical properties of SiOF-deposited PZT capacitors. The remnant polarization and leakage currents were not degraded after the deposition of SiOF. We observed that the fluorine atoms were not diffused into the metal electrode in both cases of the SiOF deposited PZT capacitors and post-deposition annealed capacitors. The SiOF films deposited in the high CF₄ flow rate exhibited rough columnar structure on the metal electrodes. We can successfully deposit SiOF in a smooth morphology by introducing TiO₂buffer layer or using the novel deposition method of changing the SiF₄ flow rate, namely two-layer-deposition method.     

Novel diffusion control process using ultra thin buffer layer for MFIS memory

Abstract

MFIS structures having excellent clear interfaces and well-crystallized ferroelectric layer were successfully fabricated by a newly developed ultra thin metal buffer layer process on SiO₂/Si. We examined the effect of sputtered Zr or ZrO₂ ultra thin films as a buffer layer for Pb_xLa_1?xTiO₃ (PLT) growth. TEM observation revealed that the buffer layer formation process in which Zr oxidized after the metal deposition had advantages to produce MFIS structures. This method is also superior for the crystallization and the control of the orientation of PLT thin film on amorphous SiO₂. Especially, for buffer layer thicknesses below 10 nm, preferred c-axis oriented PLT thin films were grown. The I-V characteristics of MFIS-FET fabricated by the proposed method showed a clear memory window due to the remanent polarization of the ferroelectric thin film. This process is the most attractive candidate for realizing MFIS structure memory.     

Improvement of the electrical properties of PZT thin films using TiO2 buffer layer

Abstract

Thin TiO₂ layers were sputter-deposited on Pt/Ti/SiO₂/Si wafers, as buffer layers for PZT thin film capacitors. It was found that TiO2 buffers of less than 4-nm-thickness could assist in obtaining highly uniform PZT thin films with no second phase. The leakage current behaviors of the PZT based capacitor are improved, while retaining the ferroelectric properties of PZT thin films such as remanent polarization and coercive field. In addition, the uniform distribution of oxygen in PZT on TiO₂/Pt indicates that the TiO₂ buffer layer act as a barrier for lead-platinum reaction, as well as for oxygen diffusion.     

Low Temperature Process for Synthesis of (100) Textured Pb(Zr0.48Ti0.52)O3 Thin Films on Si Substrate by Laser Lift-Off Transferring Technique

(100) textured Pb(Zr_0.48Ti_0.52)O₃ (PZT) films were prepared on silicon substrates by MOD process and laser lift-off technique. Textured PZT films were first grown on (001) Sapphire substrate, using Ba(Mg_1/3Ta_2/3)O₃ (BMT) materials as buffer layer. The (100) textured PZT/BMT/Sapphire films were attached to Si substrate using a transient-liquid-phase Pd-In bonding process, and then were separated from Sapphire substrates by a laser lift-off process, in which, a 38 ns pulse from excimer laser (248 nm) at 600 mJ/cm² fluence melted BMT buffer layer, expelling the Sapphire. The crystallinity of the surface of films was further improved by laser annealing. X-ray diffraction analysis of the PZT films showed that the crystallographic structure of films is maintained during laser lift-off process. Electrical testing of the films after laser lift-off process followed by laser annealing demonstrated that the ferroelectric properties are retained for the transferred films (P_r = 9μ C/cm² and E_c = 74 kV/cm).     

C-Axis Oriented MOCVD YMnO3 Thin Film and Its Electrical Characteristics in MFIS FeTRAM

Yttrium manganate (YMO) thin films were prepared on SiO₂ buffered silicon as a candidate for ferroelectric transistor random access memory (FeTRAM). The films were deposited by flash evaporated MOCVD at low temperature and post annealed to crystallize the c-axis oriented hexagonal YMO phase. It is found that oxygen content and substrate temperature are major parameters determining c-axis orientation. For the electrical characteristics, P_r (remnant polarization) ～2 μ C/cm² and ? (dielectric constant) ～ 20 are obtained in Pt/YMO/Pt structures. It is also found that a top buffer layer of 30 nm ZrO₂ helps to reduce the leakage current of Pt/top buffer/YMO/SiO₂/Si stack to 10^{? 7} A/cm² and improves the C-V memory window from 0.2 V to 2 V.     

Ferroelectric La-Sr-Co-O/Pb-La-Zr-Ti-O/La-Sr-Co-O heterostructures on silicon

Abstract

Ferroelectric Pb_0.9La_0.1Zr_0.2Ti_0.8O₃ (PLZT) thin film capacitors with symmetrical La-Sr-Co-O top and bottom electrodes have been grown on [001] Si with a Yttria stabilized zirconia (YSZ) buffer layer and on SiO₂Si substrates. A layered perovskite “template” layer (300–500 Å thick), grown between the YSZ buffer layer or the SiO₂ layer and the bottom La-Sr-Co-O electrode, is critical for obtaining the required orientation of the subsequent layers. The fatigue, retention and aging characteristics of these new structures are quite desirable for nonvolatile memory operation. Preliminary studies show that this ferroelectric performance obtained in large (50–100 μm diameter) capacitors can be replicated in smaller capacitors (down to 4 μm diameter) processed by ion milling.     

Asymmetrical single-mode silica waveguide deposited by PECVD

Silicon oxynitride (SiON) layer and SiO₂ buffer layer were deposited on silicon wafers by PECVD technique using SiH₄, N₂O and N₂. The refractive index of SiON films measured at a wavelength of 1552 nm using a prism coupler, could be continuously varied from 1.4480 to 1.4508. Optical planar waveguides with a thickness of 6 μm and a refractive index contrast (Δn) of 0.36% have been obtained. In addition, etching experiments were performed using ICP dry etching equipment on thick SiON films grown on Si substrates covered with a thick SiO₂ buffer layer. In order to measure optical properties, a polarization maintaining single-mode fiber was used for the input and a microscope objective for the output at 1.55 μ m. A low-loss and low propagation SiON-based waveguide was fabricated with easily adjustable refractive index of core layer.     

Effect of seed layer on electrical properties of Pb(Zr,Ti)O3 films grown by metalorganic chemical vapor deposition

Abstract

Pb(Zr_xTi_1?x)O₃ (PZT) ferroelectric thin films were prepared by metalorganic chemical vapor deposition (MOCVD) on Pt/Ti/SiO₂/Si substrate. Very thin PZT films, which were deposited at a lower temperature and post-annealed at higher temperature for crystallization, were used as a seed layer. PZT films grown on the seed layer exhibited superior characteristics in the crystalline structure and electrical properties, compared to those deposited without seed layer. Depending on the deposition conditions of PZT seed layer, a wide variation of surface morphology and stoichiometry was found between samples, whereas chemical composition was found to be very similar.     

Study on property variation due to the interface between PZT and electrode

Abstract

The ferroelectric capacitors are fabricated using RuO₂/Pt electrode to examine the electrode effect on ferroelectric properties. PZT films are prepared by metalorganic decomposition (MOD) on sputter deposited electrodes. In particular, inductively coupled plasma(ICP) etcher is used to minimize the etching damage. In addition, TiO₂ reaction barrier layer is also employed to retard the degradation of ferroelectric properties due to the reaction between a passivation layer and PZT film. The better hysteretic properties were obtained from Pt/RuO₂/PZT/RuO₂/Pt ferroelectric capacitors. The enhancement of ferroelectric properties is likely attributed to the modification in the microstructure of PZT film. The interfacial modification would be affected by the factors such as surface roughness, stress, and porosity of RuO₂ film. The result implies RuO₂/Pt would be a good electrode for a nonvolatile memory application.     

Epitaxial and large area PLD ferroelectric thin film heterostructures on silicon substrates

Abstract

Epitaxial thin films of Bi₄Ti₃O₁₂ and SrBi₂Ta₂O₉ have been deposited by pulsed laser deposition (PLD) onto epitaxial thin film templates of CeO₂/YSZ as well as on epitaxial electrodes of (La_0.5Sr_0.5)CoO₃, in turn deposited onto CeO₂/YSZ template layers. These electrode and buffer layers have been deposited by PLD as well. The same heterostructures, namely ferroelectric Bilayered perovskite films on the same stack of epitaxial layers, have also been deposited by large area PLD. This technique allows deposition with a good uniformity onto entire silicon 3-inch wafers. Thickness and composition uniformity of the ferroelectric films, electrodes and buffer layers are important with regard to their possible application in microelectronics. Uniformities achieved are in the range of 5 to 15% of the mean thickness, depending on the material and deposition conditions.     

Ferroelectric properties and reliability of La-Sr-Co-O/Pb-La-Zr-Ti-O/La-Sr-Co-O heterostructures on si for non-volatile memory applications

Abstract

Highly oriented La-Sr-Co-O(LSCO)/Pb-La-Zr-Ti-O(PLZT)/La-Sr-Co-O heterostructures have been successfully grown on a highly oriented Pt film which was grown on a thermally oxidized Si (SiO₂/Si) substrate. The growth of oriented Pt film on the SiO₂/Si substrate was made possible through the use of a thin bismuth titanate template layer which is c-axis oriented on the SiO₂/Si substrate. The hybrid LSCO/Pt structure effectively reduced the sheet resistance of the electrodes by at least 3–5 times compared with a single LSCO electrode. These ferroelectric PLZT capacitors on Si exhibited symmetric hysteresis loops with very desirable ferroelectric properties. The test capacitors showed reliable performance at both room and high (100°C) temperatures with respect to fatigue, retention, aging, and imprint, suggesting that they can be used as reliable, nonvolatile memory elements.     

Reduction of Leakage Current by HfO 2 High K Dielectric Film Stacked on the Ferroelectric Layer of a MFIS Structure

We report here the reduction of leakage current through a thin ferroelectric layer by insertion of an HfO 2 film. We fabricated metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) and metal-ferroelectric-insulator-metal (MFIS) structures. A Pb x La 1 m x TiO 3 (PLT) ferroelectric layer was deposited on a thermally oxidized p-type Si substrate with a Zr buffer layer. Adopting an HfO 2 layer on the ferroelectric layer of a MIFIS structure with an equivalent oxide thickness (EOT) of 5 nm resulted in a reduction by only 13 percent of the voltage distribution on the ferroelectric layer. Applying HfO 2 to the ferroelectric layer of a MFIS structure, however, led to a 70% decrease in leakage current: from 2.7 2 10 m 8 to 0.76 2 10 m 8 A/cm 2 at +1 V. An HfO 2 film, by itself, shows leakage that is 3 orders of magnitude smaller than that of PLT; clearly, insertion of the film impedes leakage through the ferroelectric layer. This characteristic is believed to contribute to extension of the retention time of MFMIS FETs.