Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.     

Study of Electron Transport in SOI MOSFETs Using Monte Carlo Technique with Full-Band Modeling

Effects of conduction-band non-parabolicity on electron transport properties in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) are studied by performing Monte Carlo simulation with a full-band modeling. An empirical pseudo-potential method is adopted for evaluating the two-dimensional electronic states in SOI MOSFETs. SOI-film thickness dependence of phonon-limited mobility, drift-velocity and subband occupancy is calculated and the results are compared with those of a simple effective mass approximation. The non-parabolicity effects are found to play an important role in 4-fold valleys under higher applied electric fields or at higher temperatures.     

Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

This paper discusses the impact of the back-gate bias on the on-state drain breakdown voltage of high-voltage silicon-on-insulator (SOI) MOSFETs. This is mandatory in order to understand the physical mechanisms behind the limitations of the safe operation area (SOA) of SOI power devices. The back-gate electrode of the SOI material will add an additional dimension to the SOA, thereby causing further reliability constraints on the circuit design. For small and negative back-gate bias, the SOA is limited by the on-state breakdown whereas the off-state breakdown sets the limit for positive back-gate bias. For the first time, an analytical model of the breakdown voltage covering the reasonable back-gate voltage range is presented providing a first step toward a closed form circuit simulation of this effect. It is shown that the back-gate potential impacts on the breakdown behavior by modulating the carrier distribution in the drift region, the base transport factor of the parasitic bipolar transistor, and the drift region resistance. Moreover, it is shown that avalanche multiplication is the limiting breakdown mechanism for lateral SOI power devices     

Subthreshold Mobility Extraction for SOI-MESFETs

Mobility calculation is a difficult task due to the stochastic nature of the particles in a device. This is especially true for a device operated in the sub-threshold region because the transport is a combination of diffusion and drift albeit diffusion dominated. As a result, one can calculate the mobility based on the drift and the diffusion techniques for a device operated in the subthreshold regime. We have developed a transport model, based on the solution of the Boltzmann Transport Equation, for modeling n-channel silicon-on-insulator (SOI) MOSFETs and MESFETs using the Ensemble Monte Carlo technique. All relevant scattering mechanisms for the silicon material system have been included in the model. The model is used to calculate both the diffusion coefficient and the drift based mobility and the results are compared with available experimental values. The mobility of the equivalent SOI MESFET device is a factor of 3–5 times higher than that of the MOSFET in the sub-threshold regime.     

Full-Band Monte Carlo Simulation of Two-Dimensional Electron Gas in SOI MOSFETs

A full-band Monte Carlo simulation of two-dimensional electron gas is performed to study effects of the non-parabolicity of the energy band structure on the phonon-limited electron mobility in SOI MOSFETs with a thin Si-layer.     

Analysis of nonequilibrium phenomena on electric characteristics of advanced MOSFETs by using a quantum energy transport model

In this paper, we have investigated nonequilibrium effects for advanced MOSFETs by using a device simulator with quantum energy transport (QET) model. The QET model allows to simulate nonequilibrium carrier transport as well as quantum confinement. The QET model includes the mobility model as a function of carrier temperature in order to consider the nonlocal effects. We have simulated advanced MOSFETs down to 20 nm gate length using the QET model. The QET model is compared with the quantum drift diffusion (QDD) model which includes a mobility model with local assumptions. It is found that the nonlocal mobility model is needed to simulate the advanced MOSFETs with less than 40 nm.     

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.     

A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench

In short-channel silicon-on-insulator metal-oxide-semiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOI MOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide.     

Study of self-heating effects in SOI and conventional MOSFETs with electro-thermal particle-based device simulator

In this paper we present a study of self-heating effects in nanoscale SOI (Silicon-On-Insulator) devices and conventional MOSFETs using an in-house electro-thermal particle-based device simulator. We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional (2D) and the three-dimensional version (3D) of the tool) and then we present a series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in SOI technology. Our simulation results for planar SOI devices (using 2D version of the tool) show that in the smallest devices considered, heat dissipation occurs in the contacts, not in the active channel region of the device. This is because of two factors: pronounced velocity overshoot effect and the smaller thermal resistance of the buried oxide layer. We propose methods in which heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. To simulate self heating in nanowire transistors, the 2D simulator was extended to three spatial dimensions. We study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel in nanowire transistors, the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel. Finally, we examine the importance of self-heating effects in conventional MOSFETs used for low-power applications. We find that the average temperature increase obtained with our simulator of about 10 K is almost identical to the value that has to be used in low-power circuit simulations.     

Study of RF Linearity in sub-50 nm MOSFETs Using Simulations

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g _m /I _d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from ?10 to ?20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (～1 V) in all devices.