Modeling of FinFET: 3D MC Simulation Using FMM and Unintentional Doping Effects on Device Operation

Novel device concepts such as dual gate SOI, Ultra thin body SOI, FinFETs, etc., have emerged as a solution to the ultimate scaling limits of conventional bulk MOSFETs. These novel devices suppress some of the Short Channel Effects (SCE) efficiently, but at the same time more physics based modeling is required to investigate device operation. In this paper, we use semi-classical 3D Monte Carlo device simulator to investigate important issues in the operation of FinFETs. Fast Multipole Method (FMM) has been integrated with the EMC scheme to replace the time consuming Poisson equation solver. Effect of unintentional doping for different device dimensions has been investigated. Impurities at the source side of the channel have most significant impact on the device performance.     

Deterioration of device characteristics of MFSFET due to fatigue

Abstract

Change of device characteristics of the metal-ferroelectric-semiconductor FET (MFSFET) with the progress of fatigue of the ferroelectric thin film are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V_G curves exhibit the accumulation, the depletion and inversion regions clearly. They also exhibit the memory window of 2V. I_D-V_D curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I_D-V_D curve is 6mA/cm², which decreases as much as 50% after fatigue. Our model is expected to be very useful in the estimation of the behaviour of MFSFET devices with the progress of fatigue.     

Integration and characterization of MFISFET using Pb5Ge3O11

Abstract

The first MFIS FETs PMOS using Pt/Pb₅Ge₃O₁₁/ZrO₂/n-Si structure has been successfully fabricated. The PGO thin film was deposited by spin on method. Single phase PGO with strong c-axis orientation and low leakage current was obtained on ZrO₂ substrate. Pt was used as top electrode and the gate stack was dry etched using chlorine chemistry. Using CMOS compatible process, the integration of MFIS FETs is simple and reliable. I_D-V_G and I_D-V_D were characterized on 10 × 10 μrn (L × W) devices. The memory window obtained is about 1.3V with 200nm PGO and 13nm ZrO₂. It is also found that memory window is less dependent on device sizes.     

Ferroelectric memory FET with Ir/IrO2 electrodes

Abstract

We proposed a MFMIS structure having a floating gate as a bottom electrode between a ferroelectric thin film and the gate SiO₂. Conventional gate SiO₂ can be used and ferroelectric thin films can be grown on bottom electrodes which have a good matching with the ferroelectric materials due to adopt the MFMIS structure. Ir and IrO₂ on poly-Si were used as floating gate. When a IrO₂ layer was formed between PZT and poly-Si, a high-quality PZT thin film was obtained and the PZT films show no fatigue up to 10¹² cycles of switching pulses. From the I_D-V_G characteristics measurement for 1·2 μm P-ch MFMIS FET, the shift in V_th or the memory window for a bias sweep of ±15V was about 3·3V. The difference of I_D-V_D curves which corresponded to I_D-V_G characteristics were found between before and after a programming pulse was applied.     

Three-Dimensional Quantum Transport Simulation of Ultra-Small FinFETs

Three-dimensional simulation based on a non-equilibrium Green’s function method including electron-phonon interaction and Si/SiO₂ interface roughness has been performed for ultra-small FinFETs. Comparing the simulated drain-current–gate-voltage characteristics with those obtained in the ballistic limit, effects of the scatterings on the device characteristics are discussed. Threshold voltage fluctuation is also discussed.     

Electrothermal Monte Carlo simulation of submicron wurtzite GaN/AlGaN HEMTs

We present results from the simulation of the electrothermal behaviour of submicron wurtzite GaN/AlGaN High Electron Mobility Transistors (HEMTs). The simulator uses an iterative procedure which couples a Monte Carlo simulation with a fast Fourier series solution of the Heat Diffusion Equation (HDE). The results demonstrate the dependence of the extent of the thermal droop observed in the I_ds-V_ds characteristics and the device peak temperature on the device bias. The paper also investigates the effect of the inclusion of thermal self-consistency on the device microscopic properties and studies the dependence of the device electrothermal characteristics on the type of substrate material used.     

RF Performance of Strained SiGe pMOSFETs: Linearity and Gain

The RF performance of strained-SiGe pMOSFETs on SOI substrates has been investigated through the use of TCAD simulations. To optimize RF performance of strained-SiGe pMOSFETs, including intrinsic gain, linearity and g_m/I_d, we propose to vary the Ge concentration in the channel, shrink the SOI thickness and adopt an asymmetric doping profile along the channel. We find that neither strain nor the asymmetric doping approach is able to unlock the trade-off between intrinsic gain and linearity found in bulk and SOI relaxed Si MOSFETs. Instead, SOI layer thickness control provides an alternative approach to improving gain without sacrificing linearity. For optimized RF performance, the strained-SiGe pMOSFETs with high Ge concentrations (0.3 ≤ x ≤ 0.7) in the channel and thin SOI layers (< 20 nm) are preferred.     

Study of RF Linearity in sub-50 nm MOSFETs Using Simulations

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g _m /I _d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from ?10 to ?20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (～1 V) in all devices.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.