改变基准电压提高A／D对输入信号分辨率的方法

本文分析了提高Ａ／Ｄ转换器对输入信号分辨率的两种途径，并提出了通过改变基准电压，在不影响采集过程的情况下，提高对输入信号分辨率的工作原理及程序框图。     

新型高速A／D转换器：改变参考电压的并—串型A／D转换器

本文分析了传统并－串比较型Ａ／Ｄ转换器存在的问题，设计了用模拟开关改变参考电压以衔接两次比较的新方案，论述了该方案的基本原理、可行性及参数指标，描绘了工作过程和特殊工作方式。     

积分电容在折线法真有效值AC/DC转换器中的作用

折线逼近抛物线法真有效值ＡＣ／ＤＣ转换技术已被国内外广泛应用到电子变换式安装电表和交流电压、交流电流变送器等量大面广产品中。本文以基于此种原理构成的０．５级交流电压变送器的实验数据为例，指出这种转换器中积分电容的取值，是决定真有效值ＡＣ／ＤＣ转换效果的关键因素。同时，还介绍了该积分电容值对变送器响应时间及纹波电压的影响情况。     

高功率因数AC／DC变换器的数字控制

对高功率因数ＡＣ／ＤＣ变换器的开关式电压调整环节,利用动态功率平衡关系,以平方输出电压作状态变量,建立离散化平均模型,在此基础上给出了闭环系统数字控制算法,仿真结果验证了所建模型及控制方法的正确性。     

电网谐波对平均值测量原理和有效值测量原理变送器的影响

用平均值ＡＣ／ＤＣ转换器测量非正弦周期信号电压和电流的有效值，存在原理性误差－－波形误差。本文定量地分析了该种误差的大小，并通过对北京地区工业用户谐波普查结果及具体波形误差计算，证明用真有效值ＡＣ／ＤＣ转换器取代平均值型ＡＣ／ＤＣ转换器已势在必行。本文虽以变送器为讨论对象，但其分析结论同样适用于其它电气测量仪器和仪表。     

大规模集成CMOS A／D转换器及应用

本文主要介绍ＭＣ １４４３３单片ＭＣＯＳ Ａ／Ｄ转换器，对芯片的双积分式Ａ／Ｄ转换工作原理进行了分析推导，给以此芯片为主体的基本数字电压表电路，并介绍了量程扩展及测量功能扩展主要方法。     

新型流水线A／D转换器原理及应用

介绍一种新型单片Ａ／Ｄ转换技术－－流水一ＡＤＣ，阐述了其结构、工作原理和性能特点，并针对使用中的一些问题出了解决方法 。     

用ADAM模块设计微机工业测控系统

在某烧结厂分布式微机测控系统的开发工作中用工业ＰＣ机构成一个二级式测控系统，在现场级使用了ＡＤＶＡＮＴＥＣＨ的数字式远程Ｉ／Ｏ模块。ＡＤＡＭ模块，有效地降低了系统成本，显著提高了系统的维护性能。     

PF66A型数字多用表

一、特点（１）采用７１３５单片ＣＭＯＳ４１２位双积分式Ａ／Ｄ转换器,选用ＬＥＤ数码管,显示清晰,亮度高。（２）准确度高,直流电压基本量程准确度达００３％。（３）交流电压及电流的测量采用真有效值（ＴＲＭＳ）ＡＣ／ＤＣ转换器,能够准确测定畸变波形的真有...     

积分电容在折线地真有效值AC／DC转换器中的作用

折线逼近抛物线法真有效值ＡＣ／ＤＣ转换技术已被国内外广泛应用到电子工安装电表和交流电压，交流电流变送器等量大面广产品中，本以基于此种原理构成０．５级交流电压变送器的实验数据为例，指出这种转换器中积分电容的取值，决定真有效值ＡＣ／ＤＣ转换效果的关键因素，同时，还介绍了该积分电容值对变送器响应时间及纹波电压的影响情况。     

A charge-sharing analog-to-digital converter with embedded downconversion using a variable reference voltage

In the field of radio receivers, downconversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the converter's performance in terms of noise and linearity. As an alternative, we propose a receiver architecture that considers the ADC as both a quantizer and a downconverter block. This is achieved through the use of a variable reference signal (in this case, a voltage), as opposed to classic time-invariant reference signals. When embedded into a charge-sharing (CS) successive approximation register (SAR) ADC, this varying reference voltage is “saved” in the digital-to-analog converter (DAC) capacitor bank during the sampling phase, preventing any conversion errors. Furthermore, a phase-locked loop (PLL) is used in order to provide an on-chip solution for the generation of this variable reference voltage, which also removes the need for dedicated bandgap circuits and reference buffers. Post-layout simulations of an 8-bit 50 MS/s CS-SAR ADC show that the proposed “embedded mixing” technique is able to downconvert a high-frequency signal while also increasing the effective resolution by around 0.5 bits, when compared with a standard DC reference voltage.     

An adaptive continuous-time incremental Σ∆ ADC for neural recording implants

In this paper, an analog-to-digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous-time (CT) incremental sigma-delta (IΣ∆) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B-noise) with 8-bit and 3-bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B-noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit-level implementation of the CT IΣ∆ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm complementary metal-oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8-bit or 3-bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1-V power supply.     

A novel flash-like all-metal-oxide semiconductor analog-to-digital converter suitable for system on chips systems

The analog-to-digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all-metal-oxide semiconductor (MOS) flash-like analog-to-digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13-μm complementary MOS (CMOS) technology with a power-supply voltage, V_DD, of 1.2 V. The simulation has been conducted on a 5-bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5-bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.     

Hybrid-mode single-slope ADC with improved linearity and reduced conversion time for CMOS image sensors

In the paper, a single-slope analog-to-digital converter (ADC) for integrated CMOS image sensor applications with an improved technique of conversion has been proposed. The proposed hybrid-mode ADC automatically uses one of the following conversion techniques: time based (i.e. PWM) or voltage based (i.e. single-slope). During the ADC operation, the clock frequency and reference voltage are modified in order to reduce the conversion time and achieve the optimal linearity. Owing to this, the pixel using a photodiode working in the integration mode achieves a linear photoconversion characteristics (irradiance to digital number), and the conversion period, which is determined by the darkest parts of a scene, is reduced by an order of magnitude comparing with known ADC solutions. The proposed conversion technique has been validated with the ASIC prototype of a CMOS imager containing photosensors integrated with the ADCs. The ASIC was fabricated in standard 0.18 μm CMOS technology. A specialized measurement system has been used to optimize linearity in the hybrid-mode conversion (integral nonlinearity below 2 LSB). The conversion period has been reduced 15 times compared with the standard technique. Measurements confirm functionality of the proposed approach, implemented within a small pixel area.     

A Proposal for Concurrent Estimation of Static and Dynamic Nonlinearity of ADC

Despite great advances in very large scale integrated-circuit design and manufacturing, performance of even the best available high-speed, high-resolution analog-to-digital converter (ADC) is known to deteriorate while acquiring fast-rising, high-frequency, and nonrepetitive waveforms. Waveform digitizers (ADCs) used in high-voltage impulse recordings and measurements are invariably subjected to such waveforms. Errors resulting from a lowered ADC performance can be unacceptably high, especially when higher accuracies have to be achieved (e.g., when part of a reference measuring system). Static and dynamic nonlinearities (estimated independently) are vital indices for evaluating performance and suitability of ADCs to be used in such environments. Typically, the estimation of static nonlinearity involves 10–12 h of time or more (for a 12-b ADC) and the acquisition of millions of samples at high input frequencies for dynamic characterization. ADCs with even higher resolution and faster sampling speeds will soon become available. So, there is a need to reduce testing time for evaluating these parameters. This paper proposes a novel and time-efficient method for the simultaneous estimation of static and dynamic nonlinearity from a single test. This is achieved by conceiving a test signal, comprised of a high-frequency sinusoid (which addresses dynamic assessment) modulated by a low-frequency ramp (relevant to the static part). Details of implementation and results on two digitizers are presented and compared with nonlinearities determined by the existing standardized approaches. Good agreement in results and time savings achievable indicates its suitability.      

Development of an analog-to-digital converter based on a neural network

The construction of an analog-to-digital converter (ADC) based on a neural network (NN) is considered. A structural diagram of the neural network and algorithms for the formation and operation of particular ADCs are proposed. Methods of self-routing of signals and improving the resiliency of the ADC NN are given for the circuit developed.     

Meeting the analog world challenge. Nyquist-rate analog-to-digitalconverter architectures

To bring digital processing and its benefits to bear on real-world applications, the analog signal of interest must be translated into a format a digital computer can utilize. This is the function of the analog-to-digital converter (ADC). After processing by a digital computer or digital signal processor (DSP), the resulting digital stream of information must be returned to its analog form by a digital-to-analog converter (DAC). The methods by which a digital code is generated within the ADC are diverse. We introduce three popular Nyquist-rate ADC architectures used today: the counter ramp ADC, the successive approximation ADC and the flash ADC     

基于VFC实现脉宽调制式A/D转换技术的研究

在分析电荷平衡型VFC转换特性的基础上,根据VFC的脉冲宽度调制特性,提出基于脉宽调制式的A/D转换新技术。基于多周期同步测量原理和校准技术,实现了高精度A/D转换。该技术方案已在科研项目中应用,取得了很好的实用效果。     

Shifting the sampled input signal in successive approximation register analog-to-digital converters to reduce the digital-to-analog converter switching energy and area

In this paper, a switching scheme is presented to reduce the capacitive digital-to-analog converter (DAC) switching energy, area, and the number of switches in successive approximation register (SAR) analog-to-digital converters (ADCs). In the proposed DAC switching method, after a few most significant bits (MSBs) decision, the sampled differential input signal is shifted into two special regions where the required DAC switching energy and area is less than the other regions. This technique can be utilized in most of the previously reported DAC switching schemes to further reduce the capacitive DAC switching energy and area. The conventional and two recently presented DAC switching techniques are utilized in the proposed SAR ADC to evaluate its usefulness.     

SoC芯片内嵌模数转换器的验证测试

如何对系统芯片(SoC)中内嵌的模数转换器进行验证测试,是集成电路测试技术研究的重点和难点之一.对一款应用于有线数字电视传输中信道解调解码芯片中内嵌模数转换器的测试方法进行了研究,在分析芯片功能和引脚的基础上,列出了具体的测试夹具开发方案和电路引线图,针对内嵌式ADC的特点,给出了测试向量中测试矢量的时序关系,根据时序...