2D‐DOA estimation performance using split vertical linear and circular arrays

This paper presents a new approach to reduce the computational complexity in two‐dimensional (2D) matrix pencil (MP) method for direction of arrival (DOA) estimation of plane wave signals using a combination of vertical uniform linear array (VULA) and uniform circular array (UCA). By applying phase mode excitation based beamforming to the UCA, we can apply the matrix pencil (MP) method to the beamspace data using only a single snapshot. The technique is based on the split array, which is composed of two perpendicular arrays. The vertical uniform linear array used to determine the elevation DOA components is located perpendicularly at the center of the uniform circular array in the horizontal plane used to calculate the azimuth angles. Unlike common planar and circular arrays, this antenna array with its particular geometry requires no pair‐matching between the azimuth and the elevation angle estimation and can also remove the drawbacks of estimation failure problems. Using this particular geometry for the 2D MP method leads to an efficient computational methodology for real‐time implementation on a digital signal processor. The obtained simulation results of the MP method applied to both uncorrelated and correlated narrow‐band sources in the presence of white noise show good performance estimation. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Performance Comparison of Scramjet‐Driven Experimental DCW‐MHD Generators with Different Cross‐Sections

The purpose of this study is to examine the influence of the shape of the cross‐section of a scramjet engine‐driven experimental diagonal conducting wall (DCW)‐MHD generator on generator performance by three‐dimensional numerical analyses. We have designed MHD generators with symmetric square and circular cross‐sections, based on an experimental MHD generator with an asymmetric square cross‐section. Under the optimum load conditions, the electric power output reaches 26.6 kW for the asymmetric square cross‐section, 24.6 kW for the symmetric square cross‐section, and 22.4 kW for the circular cross‐section. The highest output is obtained for the experimental generator with the asymmetric square cross‐section. The difference in the electric power output is induced by the difference of flow velocity and boundary layer thickness. For the generator with the asymmetric square cross‐section, the average flow velocity is highest and the boundary layer is thinnest. The compression wave is generated with dependence on the channel shape. The difference in the flow velocity and boundary layer thickness is induced by the superposition of the compression wave. © 2014 Wiley Periodicals, Inc. Electr Eng Jpn, 187(2): 9–16, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22403     

Behavior of magneto‐acoustic waves in a nonequilibrium subsonic disk MHD generator

The behavior of magneto‐acoustic waves in a nonequilibrium subsonic disk MHD generator was examined. The solution of the sixth‐order dispersion relation obtained by linearizing the set of MHD equations suggested that a magneto‐acoustic wave which propagates at a velocity of u_r ? a(u_r: radial fluid velocity, a: sound velocity) should be damped in subsonic flow. From time‐dependent quasi‐one‐dimensional simulations, it was verified that the pressure disturbance in the subsonic generator was damped at approximately the same rate as the value predicted by the linear theory. From a simplified analytical model, the mechanism of magneto‐acoustic instability with fully ionized seed was discussed, and the damping criterion for the magneto‐acoustic wave was clarified. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 142(4): 20–26, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10108     

A cascade‐connected neural model for improved 2D DOA estimation of an EM signal

This article proposes a neural network‐based approach to increase accuracy of two‐dimensional direction of arrival (DOA) estimation of an electromagnetic signal. The proposed method combines two neural networks developed using simulated and small amount of empirical data, respectively. The output of the simulation‐based neural network represents approximate information on DOAs. It is then considered as a priori knowledge for the small empirical network that is crucial for obtaining more accurate DOA estimates. The developed cascade‐connected model is validated using real data from a rectangular antenna array. Improvements in terms of accuracy and reliability are obtained and compared with the MUSIC algorithm. Copyright © 2015 John Wiley & Sons, Ltd.     

A method of new filter design based on the co‐occurrence histogram

We have proposed that the co‐occurrence frequency image (CFI) based on the co‐occurrence frequency histogram of the gray value of an image can be used in a new scheme for image feature extraction. This paper proposes new enhancement filters to achieve sharpening and smoothing of images. These filters are very similar in result but quite different in process from those which have been used previously. Thus, we show the possibility of a new paradigm for basic image enhancement filters making use of the CFI. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(1): 36–42, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20699     

Power factor improvement of single‐phase diode rectifier circuit by field‐weakening of inverter‐driven IPM motor

This paper proposes a novel inverter drive system to improve the input power factor of single‐phase diode rectifier. Conventional rectifiers need a high‐frequency switching device and a reactor to improve the input power factor. However, the proposed power converter does not need the switching device, electrolytic capacitor, or reactor. By making many ripples across the DC‐bus voltage, the input power factor can be improved. The proposed system consists of only a single‐phase diode rectifier, small film capacitor, three‐phase inverter, and motor. The proposed system adopts an interior permanent magnet (IPM) synchronous motor. The IPM motor is well known as a high‐efficiency motor and can realize field weakening. The basic ideas of the inverter control method are based on the following operations: the inverter's controlled synchronous with the DC‐bus ripple voltage by field‐weakening method, and direct active power feeding from the source side to the motor without smoothing the DC‐bus voltage. This paper describes that the proposed method can obtain an input power factor of 97.3% by experimental tests, and realizes the goals of small size and long life of the system. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 152(2): 66–73, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20047     

Carrier‐envelope phase‐stabilized chirped‐pulse amplification system

We demonstrated a carrier‐envelope phase (CEP) stabilized chirped‐pulse amplifier system. This amplifier system is composed of grating based pulse‐stretcher and compressor, a regenerative amplifier and a multi‐pass amplifier. We employed a new pulse‐pick‐up method to select CEP stabilized seed pulses. This pulse selection method is different from established practice which is based on pulse train timing, but is based on CEP of seed pulse. We measured amplitude‐to‐phase noise conversion coefficient of microstructure fiber and evaluated the additional out‐of‐loop error of carrier‐envelope offset (CEO) control. We also investigated the effect of beam pointing of the measured fringe shift in self‐referencing spectral interference method. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(3): 35–42, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20334 Copyright © 2006 Wiley Periodicals, Inc.     

Technologies and applications of Al‐free high‐power laser diodes

We report high‐power technologies in 0.8‐µm Al‐free InGaAsP/InGaP laser diodes. To realize the high‐power operation, the improvement of catastrophic optical mirror damage (COMD) power density level is required. In addition to the use of low surface recombination velocity of Al‐free materials, optimization of waveguide thickness in broad waveguide structure with tensile‐strained barriers and current blocking structure near facets has led to high COMD power density level. Highly stable operation of Al‐free laser diodes with these structures has been obtained over 2500 hours at 2 W from a stripe width of µm. Applications of high‐power laser diodes are also described. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 158(1): 53–59, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20286     

Numerical simulation of blow‐down closed‐cycle disk MHD generator

Numerical simulations of the closed‐cycle disk MHD generation experiment with Tokyo Institute of Technology's Fuji‐1 blow‐down facility are performed. In the calculations, the r–z two‐dimensional time‐dependent simulation code developed by the authors that can take the effect of water contamination into account is used, and the experimental conditions of Run A4109 operated by Disk‐F4 generator are selected as the numerical conditions. When the water contamination is the lowest level realized in the experiments, the simulation results coincide with the experimental results reasonably well, though there exist some discrepancies caused by inaccuracy of used basic plasma parameters, limitations of the two‐dimensional approximation, and so on. The voltage–current curve is almost linear, indicating that the MHD interaction is relatively weak and the flow field is mainly determined by the back‐pressure. The increase of the water contamination level results in decreased seed ionization rate at the generator channel inlet, leading to the steep deterioration of the generator performance. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 148(2): 46–54, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10335     

Magnetic properties of PLD‐fabricated ND‐Fe‐B film magnets and their applications to millimeter‐size motors

We succeeded in depositing 200‐ to 300‐µm‐thick Nd‐Fe‐B film magnets with (BH)_max of approximately 55 kJ/m³ on Fe substrates by the PLD method. In addition, we confirmed that a millimeter‐size motor, which was prepared from the obtained film, rotates at 15,160 rpm under a no‐load test. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 159(2): 1–6, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20215     

Magnetic properties of Pr‐Fe‐Co‐V‐W‐Si‐B system exchange spring magnets

The melt‐spun ribbons of Pr‐Fe‐Co‐V‐W‐Si‐B system alloys were prepared by single roller rapid‐quenching method. The effects of composition, surface velocity, and heat treatment on the magnetic properties were investigated. The P₉sFe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 alloy ribbons prepared at a surface velocity of 12.5 m/s were crystallized by heat treatment, and the optimum heat‐treatment condition was found to be at 575°C for 3 min, for which the magnetic properties were (BH)_max = 136.1 kJ/m³, J_r = 0.93 T, H_cJ = 652.2 kA/m, and H_cB = 528.3 kA/m. The temperature coefficients of J_r and H_cJ for the ribbons crystallized from melt‐spun ribbons of Pr₉Fe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 alloy were α(J_r)_ave = ?0.057%/°C and α(H_cJ) = ?0.450%/°C. The value of (B)_max for the compression molding Pr₉Fe₇₁Co₈V_0.5W_0.5Si_0.5B_10.5 isotropic bonded magnet prepared by using the ribbons annealed at 575°C for 3 min is 80.0 kJ/m³, and the density is 6.24 Mg/m³. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(3): 10–16, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20211 Copyright © 2006 Wiley Periodicals, Inc.     

A fuzzy‐based control method for smoothing power fluctuations in substations along high‐speed railways

The use of superconducting magnetic energy storage (SMES) for smoothing power fluctuations in a railway substation has been discussed. This paper proposes a smoothing control method based on fuzzy reasoning for reducing the SMES capacity at substations along high‐speed railways. The proposed smoothing control method comprises three countermeasures for the reduction of the SMES capacity. The first countermeasure involves modification of rule 1 for smoothing out the average electric power to its average values. The other countermeasures involve the modification of the central value of the stored energy control in the SMES and revision of the membership function in rule 2 for the reduction of the SMES capacity. The SMES capacity in the proposed smoothing control method is reduced by 49.5% compared to that in the nonrevised control method. Computer simulations confirm that the proposed control method is suitable for smoothing out power fluctuations in substations along high‐speed railways and for reducing the SMES capacity. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 179(2): 35–43, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21175     

Fast settling frequency synthesizer with two‐point channel control paths

A frequency synthesizer with low‐power and very short settling time is introduced, which utilizes two‐point channel control paths. While the main‐path is the same as normal channel controls, a digital‐to‐analog converter (DAC) with tunable gain is used for the compensation‐path to form a feed‐forward direct voltage‐controlled oscillator (VCO) control path. When the two paths are ideally matched, the two‐point control can show zero settling time regardless of the amount of frequency change. However, the settling time performance can be significantly degraded if there exists any mismatch between the two paths. In order to remove the mismatch, a simple compensation method combining a linearized VCO with a resistor‐loaded tunable DAC is presented. We show that the overall mismatch can be effectively tuned out by controlling the DAC load resistor, since the mismatch caused by process–voltage–temperature variations is dominated by the resistor variation. We have achieved near‐zero settling time for 75thinspaceMHz frequency jumping from 2.4 GHz even with the use of narrow phase‐locked loop (PLL) bandwidth of 20 kHz. When the phase noise at 1 MHz offset from 2.4 GHz is ? 116.6dBc/ Hz, the total PLL power consumption using 0.18 µm CMOS technology is only 4.2 mW. Copyright © 2011 John Wiley & Sons, Ltd.     

Development of a high‐pressure air‐insulated 72/84‐kV disconnecting switch corresponding to bus‐transfer current switching

SF₆ gas has excellent dielectric strength and current interruption performance. For these reasons, it has been widely used for gas‐insulated switchgear (GIS). Today, such global environmental problems as global warming are important issues of concern. SF₆ gas is known as a greenhouse gas with a long atmospheric lifetime, and has global warming potential of 23,900. SF₆‐free 72‐kV GIS was recently developed by using high‐pressure air and a gas/solid hybrid structure. But an alternating current disconnecting switch (DS) has yet to be developed thus making this type of SF₆‐free 72‐kV GIS unsuitable for double bus‐bar application. Consequently, the development of a high‐pressure air‐insulated DS corresponding to bus‐transfer current switching has been expected. The bus‐transfer current is the highest among all current interruption requirements for the DS. To develop an alternating current DS, efforts must be made to reduce arcing damage to the electrode. This paper describes the fundamental characteristics of current interruption in the plain break type and the magnetic field driven type. Then, average arcing time of the magnetic field driven type was estimated by magnetic flux density. Finally, two types of DS, which were a high‐speed plain break and a low‐speed magnetic field driven, were confirmed to comply with bus‐transfer current switching requirements on JEC standard. © 2009 Wiley Periodicals, Inc. Electr Eng Jpn, 167(2): 48–55, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20595     

High‐speed and high‐precision position control using a sliding mode compensator

To achieve high‐speed, high‐precision position control for semiconductor product machines and industrial robots, full‐closed feedback control is applied. Many control methods have been proposed for such a system. In general, proportional position control and proportional plus integral velocity control or integral plus proportional velocity control (P,PI/I‐P), which is a type of proportional plus integral plus differential control (PID), is applied in many industrial applications. However, in the case of changing mechanical characteristics of the control target, the parameters of P,PI/I‐PI control must also change in order to maintain good motion performance. In this paper, we propose a new P,PI/I‐P control method that includes a nonlinear compensator. The algorithm of the nonlinear compensator is based on sliding mode control with chattering compensation. The effectiveness of the proposed control method is evaluated using a full‐closed single‐axis slider system via point‐to‐point control and contour control in the case of changing load. The experimental results indicate that the proposed control method is robust in the case of changing acceleration/deceleration of control reference, changing load, and low‐velocity contour motion. © 2010 Wiley Periodicals, Inc. Electr Eng Jpn, 174(2): 65–71, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21011     

FPGA‐based implementation for improved control scheme of grid‐connected PV system with 3‐phase 3‐level NPC‐VSI

The large scale penetration of renewable energy resources has boosted the need of using improved control technique and modular power electronic converter structures for efficient and reliable operation of grid‐connected systems. This study investigates the performance of a grid‐connected 3‐phase 3‐level neutral‐point clamped voltage source inverter for renewable energy integration by using improved current control technique. For medium or high‐voltage grid interfacing, the multilevel inverter structure is generally used to reduce the voltage stress across the switching device as well as the harmonic distortion. The neutral‐point clamped voltage source inverter is controlled by using decoupling technique along with the proper grid synchronization via moving average filter–based phase‐locked loop. The moving average filter–based phase‐locked loop is used to reduce the delay in grid angle estimation under balanced as well as distorted grid conditions. A Lyapunov‐based approach for analysing the stability of the system has also been discussed. In this study, the hardware‐in‐loop (HIL) simulation of the control algorithm and the grid synchronization technique is realized using Virtex‐6 FPGA ML605 evaluation kit. The performance of the system is analyzed by conducting a time‐domain simulation in the Matlab/Simulink platform and its performance is examined in the HIL environment. The simulation and the hardware cosimulation results are presented to validate the effectiveness of the proposed control scheme.     

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

Impact of stray inductances of the power loop on false trigger‐on in the zero‐voltage‐switching full‐bridge converter

Here, we propose an exhaustive theoretical investigation and experimental verification of the false trigger‐on phenomenon, which would lead to the interaction between the upper and lower devices during the switching transient, in the zero‐voltage‐switching (ZVS) full‐bridge converter. An equivalent model of the converter, which takes not only the parasitic capacitors of the metal–oxide–semiconductor field‐effect transistors into account but also the stray inductances of the main circuit, is presented. Based on the model, a comprehensive study of the false trigger‐on phenomenon is carried out. According to the analysis results, the stray inductances of the metal–oxide–semiconductor field‐effect transistors have negligible influence on the false trigger‐on phenomena since the soft‐switching is realized. The false trigger‐on phenomenon is induced by the stray inductances of the main circuit. Moreover, the arrangement of the switching sequence would cause significant discriminations in the false trigger‐on phenomena because of the specific working mode of the ZVS full‐bridge converter. According to the investigation results, optimization methods are presented to suppress the induced voltage. At last, the theoretical investigations are verified by tests of a ZVS full‐bridge converter. Copyright © 2016 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.