基于改进 U-Net 网络的眼底血管图像分割研究

针对眼底血管图像存在血管细小、视网膜病变而导致分割精度低的问题,提出了一种引入残差块、级联空洞卷积、嵌入注意力机制的U-Net视网膜血管图像分割模型.首先采用提高视网膜图像分辨率,以点噪声为中心、512为边长裁剪来扩增数据集,然后在U-Net模型中引入残差块,增加像素特征的利用率和避免深层网络的退化;并将U-Net网络的底部替换为级联空洞卷积模块,扩大特征图的感受野,提取更丰富的像素特征;最后在解码器中嵌入注意力机制,加重目标特征的权重,减缓无用信息的干扰.基于CHASE数据集的实验结果表明,所提模型的准确率达到了98.2％,灵敏度达到了81.72％,特异值达到了98.90％,与其他多尺度神经网络方法相比体现了更好的分割效果,充分验证了提出改进的U-Net网络模型能有效提高血管分割精度、辅助确诊血管病变.     

Real-time removal of impulse noise from MR images for radiosurgery applications

In the recent years, image processing techniques are used as a tool to improve detection and diagnostic capabilities in the medical applications. Among these techniques, medical image enhancement algorithms play an essential role in the removal of the noise, which can be produced by medical instruments and during image transfer. Impulse noise is a major type of noise, which is produced by medical imaging systems, such as MRI, computed tomography (CT), and angiography instruments. An embeddable hardware module, which can denoise medical images before and during surgical operations, could be very helpful. In this paper, an accurate algorithm is proposed for real-time removal of impulse noise in medical images. Our algorithm categorizes all image blocks into three types of edge, smooth, and disordered areas. A different reconstruction method is applied to each category of blocks for noise removal. The proposed method is tested on MR images. Simulation results show acceptable denoising accuracy for various levels of noise. Also, an field programmable gate array (FPGA) implementation of our denoising algorithm shows acceptable hardware resource utilization. Hence, the algorithm is suitable for embedding in medical hardware instruments such as radiosurgery devices.     

Digital implementation of biologically inspired Wilson model,population behavior,and learning

Spiking neurons, as a computational unit, are the main part in biological information processing systems. This paper presents a digital hardware implementation of a biological neuron on a field‐programmable gate array due to its high accuracy and high speed, especially for large‐scale simulations which is a key objective in the neuromorphic research field. Although this is a computationally expensive task, the use of more biological realistic system results in higher accuracy in mimicking biological behaviors of neural networks. Given that, the Wilson model is one of the most important biological neuron models that can be used in the architecture of spiking neural networks. To be closer to biological systems, a method is proposed to test the possibility of implementation of the Wilson neuron model on digital platforms. The results of the hardware implementation of the Wilson neuron and a spiking network on a field‐programmable gate array, capable of character recognition with supervised learning algorithm, are presented in this paper; moreover, population behavior of this model is simulated. In large‐scale implementation of 2000 Wilson neuron model, population capability, feasibility, and costs are investigated. This paper presents a method to the implementation of Wilson neurons on digital platforms, suggesting that the available system is an attainable platform for the implementation of large‐scale biologically plausible neural networks on field‐programmable gate array devices. Hardware synthesis, physical implementation on field‐programmable gate array, and theoretical analysis confirm that the proposed model has hardware so that makes it an appropriate model for the large‐scale digital implementation.     

A distributed arithmetic hardware architecture for real-time hough-transform-based segmentation

Real-time segmentation and tracking of biopsy needles is a very important part of image-guided surgery. Since the needle appears as a straight line in medical images, the Hough transform for straight-line detection is a natural and powerful choice for needle segmentation. However, the transform is computationally expensive and in the standard form is ineffective for real-time segmentation applications. This paper proposes a dedicated hardware architecture for the Hough transform based on distributed arithmetic (DA) principles that results in a real-time implementation. The architecture exploits the inherent parallelism of the Hough transform and reduces the overall computation time. The DA Hough transform architecture has been implemented using the Xilinx field-programmable gate array (FPGA). For a 256x256-bit image, the proposed design takes between 0.1 ms and 1.2 ms to process the Hough transform when the feature points in the image are varied from 2% to 50% of the total image; these values are well within the bounds of real-time operation and thus can facilitate needle segmentation in real time.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

A reconfigurable real-time neuromorphic hardware for spiking winner-take-all network

The central nervous system receives a vast amount of sensory inputs, and it should be able to discriminate and recognize different kinds of multisensory information. Winner-take-all (WTA) consists of a simple recurrent neural network carrying out discrimination of input signals through competition. This paper presents a real-time scalable digital hardware implementation of the spiking WTA network. The need for concurrent computing, real-time performance, proper accuracy, and the reconfigurable device has led to the field-programmable gate array (FPGA) as the target hardware platform. A set of techniques is employed to lessen memory and resource usage. The proposed architecture consists of multiprocessing elements, which share hardware resources between a specific number of neurons. We introduce a novel connectivity array for neurons (dedicated to the WTA network) to cut down memory usage. Also, a multiplier-less method in the neuron model and a novel tree adder in the synapse processing unit are designed to improve computational efficiency. The proposed network simulates 4,500 neurons in real time on a Xilinx Artix-7 FPGA, while a scalable architecture facilitates the implementation of up to 20,000 neurons on this device. The pipeline structure can guarantee real-time performance for large-scale networks. Based on simulation and physical synthesis results, the presented network mimics biological WTA dynamics and consumes efficient hardware resources.     

Robot vision with cellular neural networks: a practical implementation of new algorithms

Cellular neural networks (CNNs) are well suited for image processing due to the possibility of a parallel computation. In this paper, we present two algorithms for tracking and obstacle avoidance using CNNs. Furthermore, we show the implementation of an autonomous robot guided using only real‐time visual feedback; the image processing is performed entirely by a CNN system embedded in a digital signal processor (DSP). We successfully tested the two algorithms on this robot. Copyright © 2006 John Wiley & Sons, Ltd.     

基于卷积神经网络的生产日期识别

为了提高识别效率并减少人工成本,采用深度学习的方法对生产日期图像进行识别。首先对生产日期图像进行预处理,使用水平投影分割算法并提出一种区域最大值分割的方法将图像中的干扰字符去除,只留下数字、字母和汉字字符。然后创建一个由生产日期图像中常包含的数字、英文、汉字字符所组成的可扩展的数据集。最后构建一个卷积神经网络模型并将数据集送入训练以获得较高的识别准确率。经测试基于卷积神经网络的识别方法对生产日期识别的准确率高达98%。     

基于自组织小波神经网络的磁共振图像分割方法

磁共振图像的准确分割对于辅助医生确定病灶的位置和形状、制订治疗方案和评价治疗效果具有重要的意义。本文提出了一种新的磁共振图像（MRI）分割方法。构造了一种自组织小波神经网络,通过融合T1、r12和Pd图像的特征来识别MRI中生物组织的类别。该网络继承了小波分析局部精度高和神经网络自学习能力强的优点,采用自组织算法利用训练数据的稀疏性对网络的结构和初始参数进行优化,简化了网络结构,提高了网络学习的速度,避免了网络陷入局部最优学习。将所提方法应用于大脑磁共振图像分割的实验结果表明,所设计的自组织小波神经网络MRI图像分割方法具有精度高和学习速度快的优点。     

Pixel‐level snakes on the CNNUM: algorithm design,on‐chip implementation and applications

In this paper, a new algorithm for the cellular active contour technique called pixel‐level snakes is proposed. The motivation is twofold: on the one hand, a higher efficiency and flexibility in the contour evolution towards the boundaries of interest are pursued. On the other hand, a higher performance and suitability for its hardware implementation onto a cellular neural network (CNN) chip‐set architecture are also required. Based on the analysis of previous schemes the contour evolution is improved and a new approach to manage the topological transformations is incorporated. Furthermore, new capabilities in the contour guiding are introduced by the incorporation of inflating/deflating terms based on the balloon forces for the parametric active contours. The entire algorithm has been implemented on a CNN universal machine (CNNUM) chip set architecture for which the results of the time performance measurements are also given. To illustrate the validity and efficiency of the new scheme several examples are discussed including real applications from medical imaging. Copyright © 2005 John Wiley & Sons, Ltd.