Buck变换器电流和电压跟踪型软起动电路设计

提出了电流跟踪型和电压跟踪型两种软起动方式的概念,分析了其工作原理.介绍了两种新型的电压跟踪型外部软起动电路,即前馈电容软起动电路和基于外部运算放大器软起动电路.阐述了这两种电路的工作原理和优缺点,并详细说明了它们的设计方法.同时介绍了3种常用的基于二极管或三极管电流跟踪型外部软起动电路.最后给出了相火的测试结果和实验的波形.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis and simulation of distributed T/H with averaging technique in folding and interpolating A/D converters

Distributed track‐and‐hold (T/H) circuit is widely used in folding and interpolating analog‐to‐digital (A/D) converters as a good candidate of single T/H circuits for an optimum overall system performance. But, rigorous analysis and method for design do not exist. This paper brings averaging network to suppress the random offset voltages of the differential difference pre‐amplifiers (DDPAs), which locate before T/H circuit featuring two differential inputs for the requirement of fully differential A/D converters. The first contribution of this work is to present the exact expressions for the output voltage and gain in S‐domain, the integral nonlinearity (INL) and differential nonlinearity (DNL) in DDPAs through the further insight into this architecture. Furthermore, distortion resulting from settling time limitation, interpolation error, folder offset, and all sources of mismatch in averaged DDPAs is considered. In addition, the figure of merit for INL and DNL is proposed to quantify the effectiveness of averaging and be served as the guideline for the optimum design. Finally, these theoretical results were verified against Hspice simulations from a design example of distributed T/H circuits for 8‐bit 250 MHz folding and interpolating A/D converter, which confirmed the accurate and exhaustive analysis and exhibited a good agreement. Copyright © 2009 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

Energy-efficient algorithms for assessment of the rail-circuit operation

The voltage in a rail circuit is determined for reliable detection of the mobile unit or a train on the section of the railway track. It is proposed to use the structures of the automatic block system based on the time-division channels of status scanning of the rail circuits with subsequent signal processing by two parameters. The first parameter includes the assessment of correspondence of the code signals transmitted to the rail circuit and received from the rail circuit. The second parameter is obtained based on the analysis of the voltage at the rail-circuit output within the current and previous measurements considering the voltagechange rate. This latter parameter makes it possible to distinguish reliably the state when the rail track is occupied by the train from the random changes of the rail-circuit parameters from the influence of the external factors. The proposed algorithms permit one to reduce significantly consumption of electric energy providing operation of rail circuits.     

A small fully digital open‐loop clock and data recovery circuit for wired BANs

This paper proposes a new open‐loop and low complexity (small size) fast‐lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open‐loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase‐locked loops or delay‐locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non‐return‐to‐zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal‐oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35‐data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.     

Progress in optical modulation formats for high-bit rate WDM transmissions

With the progress of optical communication systems, and especially the constraints brought by wavelength division multiplexing (WDM) transmissions and increased bit rates, new ways to convert the binary data signal on the optical carrier have been proposed. It appears clearly now that several of the methods proposed by research laboratories will be applied into commercial products soon due to the large improvements generated. This paper intends to summarize some of the most interesting proposed modulation formats for high bit rate (especially 40 Gb/s) WDM transmissions.     

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed‐signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit‐matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit‐string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide‐based flat scheme is developed to transform an absolute co‐ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation‐decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. Copyright © 2005 John Wiley & Sons, Ltd.     

基于快速检测和速断控制的智能断路器毫秒级保护方案

在低压配电系统中,保护的准确性及实时性直接影响着电力部门和用户的安全及切身利益。智能断路器通过快速跟踪检测技术,对线路短路进行实时监测,并对故障进行快速响应处理。通过对短路突变信息进行奇异性检测分析,提高了保护的准确性与可靠性。基于快速跟踪检测技术的速断控制方法在低压智能断路器可以为需要快速保护的线路或节点提供可靠快速的保护,可以与传统监控系统配合使用,实现低压台区保护功能的升级,也可按台区智能管控的要求进行建设,实现低压台区智能快速保护的目标。通过在现场实际应用,对于大电流短路故障的快速保护响应都能够在18mS内完成,达到了预期的效果并验证了方案的可行性与实用性。     

TTL六值“与非”门与七态门电路的研究

根据TTL六值门电路有 5个信号检测阈值的特点 ,借鉴二值门电路的置阈方法 ,设计了 1种TTL六值“与非”门电路和 1种七态门电路 .这 2个电路均通过实验证明 :电路工作稳定 ,性能可靠 ,且具有驱动负载能强等特点 .