超低导通电阻Ron的SiC沟槽器件

本文介绍了下一代碳化硅(SiC)平面MOSFET、沟槽结构肖特基二极管和沟槽MOSFET器件。首先,开发了SiC平面MOSFET,可以抑制在正向电流通过时引起寄生PN结二极管的劣化;其次,开发了新型沟槽SiC肖特基二极管,与传统SiC二极管相比,在可接受的漏电流条件下,具有更低的正向压降;第三,开发了新型双沟槽结构SiCMOSFET,在保持超低导通电阻的同时,提高了器件的可靠性,其主要原因在于新结构有效降低了槽栅底部的最大电场强度,抑制了栅氧的击穿。     

SiC MOSFET开关特性及多等级栅电压驱动电路

针对新型宽禁带功率半导体器件碳化硅(SiC)金属-氧化物半导体场效应晶体管(MOSFET),为了充分发挥其在高功率密度和高效率应用场合中的高速及低功耗特性,分析了SiC MOSFET的开关特性,提出了一种基于复杂可编程逻辑器件(CPLD)的新型多等级栅电压驱动电路(MGD)。在SiC MOSFET开关不同阶段,通过调整栅极驱动电压以改善其开关特性。与传统驱动电路(CGD)相比,提出的MGD在相同门极驱动电阻与栅源极电容前提下,能有效提高开关速度,降低电压电流尖峰、降低开关损耗。最后通过双脉冲实验,分析了栅极驱动电阻,栅源极电容对开关特性的影响,验证了MGD在改善开关特性方面具有明显的优越性。     

双扩散型MOSFET栅电阻测试实现与应用

功率MOSFET的开关性能主要取决于栅极和源极间的等效电阻Rg和等效电容Ggs的乘积.讲述了双扩散型MOSFET栅电阻Rg和栅电容Cgs的等效模型和构成,介绍了金属绝缘半导体结构C-V曲线及栅电阻Rg的测试方法和设备.通过选用不同的直流偏置电压、频率、信号幅值等进行测试,确定了比较合适的栅电阻Rg测试方法.栅电阻Rg测试还可以用于生产中的不良分析.     

功率MOSFET寄生电容劣化对开关瞬态响应的影响

为解决功率MOSFET寄生电容劣化影响寿命的问题,在MOSFET非线性模型基础上,深入分析MOSFET寄生电容参数和开关管瞬态响应信号之间的关系,推导了各参数和瞬态响应之间的关系表达式,并用Saber仿真实验进行验证。由于栅极对MOSFET的性能影响至关重要,所以此次实验分析了和栅极相关的栅源电容Cgs和栅漏电容Cgd。结果表明,在寄生参数相同劣化程度时,栅源电容对瞬态响应的影响达到7.08%,而栅漏电容近似只有1.6%。栅源电容的劣化更大程度上影响瞬态响应,为MOSFET劣化提供了新的研究思路。     

面向低压高频开关应用的功率JFET的功耗

提出了一种埋氧化物槽栅双极模式功率JFET(BTB-JFET),其面向低压高频开关应用。首次通过仿真对BTB-JFET、常规的槽栅双极模式JFET(TB-JFET)和槽栅MOSFET(T-MOSFET)等20V级的功率开关器件在高频应用时的功率损耗进行了比较。仿真中借鉴现有的高性能T-MOSFET的结构尺寸,并采用了感性负载电路对器件进行静态以及混合模式的电特性仿真,结果表明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小25%;当工作频率为1MHz和2MHz时常开型TB-JFET与T-MOSFET相比总功耗分别降低了14%和19%,而常开型BTB-JFET较TB-JFET的总功耗又进一步降低了6%。仿真结果还表明,在不同工作频率下,常闭型JFET的性能都不如T-MOSFET。样管初步测试结果证明,常开型BTB-JFET与TB-JFET相比,零偏压时栅漏电容CGD减小45%,与仿真结果相一致。     

高速集电极沟槽绝缘栅双极晶体管

在前期高速绝缘栅双极晶体管(IGBT)的基础上提出一种高速集电极沟槽绝缘栅双极晶体管(CT-IGBT)。该器件沟槽集电极与漂移区的内建电势差感应形成电子沟道而加快关断速度,且集电极沟槽具有不同于传统电场截止层(FS)的电场截止机制,并引入低浓度N型层以降低集电极沟槽对空穴注入的抑制作用。硅基材料有限元仿真结果表明,新结构CT-IGBT的关断下降时间比传统沟槽FS-IGBT少49%,且前者耐受的雪崩能量比后者高32%。因此,新结构CT-IGBT具有比FS-IGBT更优越的关断速度和强度,可应用于大功率高速电力电子系统。     

4 500 V沟槽栅IGBT芯片的设计与研制

为提升IGBT单芯片的电流密度,掌握高压沟槽栅IGBT技术,进行4500 V沟槽栅IGBT芯片的研制。使用TCAD仿真软件,对4500 V沟槽栅IGBT的衬底材料、载流子储存层设计、沟槽宽度、沟槽深度、假栅结构等方面进行研究和仿真分析,明确各方面设计与芯片性能的关系。根据总体设计目标,确定相应的芯片结构和工艺参数,并对4500 V沟槽栅IGBT芯片进行流片验证。验证结果显示：4500 V沟槽栅IGBT芯片的测试结果符合设计预期,芯片的额定电流、导通压降、开通损耗和关断损耗等关键参数相比平面栅IGBT芯片有明显优化。     

选择区域外延槽栅结构GaN常关型MOSFET的研究

高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。     

4 500 V沟槽栅IGBT芯片的设计与研制

为提升IGBT单芯片的电流密度,掌握高压沟槽栅IGBT技术,进行4500 V沟槽栅IGBT芯片的研制。使用TCAD仿真软件,对4500 V沟槽栅IGBT的衬底材料、载流子储存层设计、沟槽宽度、沟槽深度、假栅结构等方面进行研究和仿真分析,明确各方面设计与芯片性能的关系。根据总体设计目标,确定相应的芯片结构和工艺参数,并对4500 V沟槽栅IGBT芯片进行流片验证。验证结果显示：4500 V沟槽栅IGBT芯片的测试结果符合设计预期,芯片的额定电流、导通压降、开通损耗和关断损耗等关键参数相比平面栅IGBT芯片有明显优化。     

桥式电路中不同封装SiC MOSFET串扰问题分析及低栅极关断阻抗的驱动电路

由于SiC MOSFET开关速度较快,使得桥式电路中串扰问题更加严重,这样不仅限制了SiC MOSFET开关速度的提升,也会降低电力电子装置的可靠性。针对SiC MOSFET的非开尔文结构封装和开尔文结构封装的串扰问题分别进行分析,栅漏极结电容的充放电电流和共源寄生电感电压均会引起处于关断状态开关管的栅源极电压变化。提出一种用于抑制串扰问题的驱动电路,该驱动电路具有栅极关断阻抗低、结构简单、易于控制的特点。分析该驱动电路的工作原理,提供主要参数的计算方法。最后通过实验测试了两种结构封装SiC MOSFET的串扰问题,并且对提出的驱动电路进行了实验,验证了其正确性以及对串扰问题的抑制效果。     

Safe Operating Area Considerations for Integrated Trench-Based Power Devices

This paper discusses the hot-carrier and electrical safe operating area (SOA) of trench-based integrated power devices. The hot-carrier SOA is determined by the avalanche current, exhibiting a maximum at intermediate drain voltage. The initial hot-carrier degradation is dependent on the crystal plane on which the gate oxide is grown. During hot-carrier stress, interface states are formed in the device's accumulation region. No channel degradation is observed. The electrical SOA of the trench-based MOS (TB-MOS) is much larger than a comparable lateral DMOS (LDMOS) or vertical DMOS (VDMOS). Even for 100-ns pulses, the TB-MOS exhibits electrothermal effects, contrary to LDMOS and VDMOS. Finally, the intrinsic gate oxide quality of the trench gate oxide is reported on. It is proven that the oxide time-dependent dielectric breakdown is determined by the thinnest oxide along the trench sidewall.      

低干扰低损耗新型MOSFET三阶驱动电路

由于金属氧化物半导体场效应晶体管(MOSFET)存在开关速度快、驱动容易等特点，故在变流电路中大量使用，但由此而产生的电磁干扰也越来越严重。驱动电路作为功率单元与控制电路的接口，其性能对电磁干扰的影响十分重要。该文在对MOSFET开关暂态过程进行详细地分析后，提出一种新的驱动电路，该驱动电路在不影响开关速度的情况下可以减小电磁干扰及开关损耗，而且该驱动电路与传统驱动电路相比仅需增加几个额外的低压器件，易于实现。文中最后给出了三阶驱动电路与其它几种不同驱动电路开通与关断时的电压电流波形及相应的传导发射。实验结果表明该驱动电路电磁干扰小，功率损耗低，开关速度快，无电压及电流的过冲现象，实现了驱动电路的优化。     

沟槽栅场终止型IGBT瞬态数学模型

沟槽栅场终止型代表了绝缘栅双极型晶体管(IGBT)的最新结构。由于沟槽栅结构与平面栅结构在基区载流子输运、栅极结电容计算等方面存在较大的不同,沿用平面栅结构的建模方法不可避免会存在较大的偏差。基于对沟槽栅场终止型IGBT结构特点及模型坐标系的分析,考虑载流子二维效应将基区分成PNP和PIN两部分,根据PIN部分的沟槽栅能否被PNP部分的耗尽层覆盖分析了栅极结电容计算方法,提出一种沟槽栅场终止型IGBT瞬态数学模型,并进行仿真与实验验证。     

A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench

In short-channel silicon-on-insulator metal-oxide-semiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOI MOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide.     

Rated overload Characteristics of IGBTs for low-voltage and high-voltage devices

By a vertical shrink of the nonpunchthrough insulated gate bipolar transistor (NPT IGBT) to a structure with a thin n-base and a low-doped field stop layer a new IGBT can be realized with drastically reduced overall losses. In particular, the combination of the field stop concept with the trench transistor cell results in an almost ideal carrier concentration for a device with minimum on-state voltage and lowest switching losses. This concept has been developed for IGBTs and diodes from 600 V up to 6.5 kV. While the tradeoff behavior (on-state voltage V/sub CEsat/ or V/sub F/ to tail charge) and the overall ruggedness (short circuit, positive temperature coefficient in V/sub CEsat/, temperature independence in tail charge, etc.) is independent of voltage and current ratings the switching characteristics of the lower voltage parts (blocking voltage V/sub Br/<2 kV) is different in handling to the high-voltage transistors (V/sub Br/>2kV). With the HE-EMCON diode and the new field stop NPT IGBT up to 1700 V there is almost no limitation in the switching behavior, however, there are some considerations-a certain value in the external gate resistor has to be taken. High-voltage parts usually have lower current density compared to low-voltage transistors so that the "dynamic" electrical field strength is more critical in high-voltage diodes and IGBTs.     

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

门极换流晶闸管关键技术的研究

通过对门极换流晶闸管(GCT)关键技术的研究,提出了一种沟槽隔离的逆导型GCT结构.借助MEDICI软件,模拟了GCT的各项特性及其在内部的微观现象,对透明阳极、缓冲层、隔离区等关键结构参数进行了优化设计,并对其制作工艺进行分析.研究结果表明,采用透明阳极、缓冲层和沟槽隔离的逆导型GCT结构,不仅可以获得更好的静、动态性能,而且可大大降低制作工艺难度,有望在国内现有工艺装备下进行开发.