Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters

In this paper, a two‐dimensional dynamic element matching digital to analog converter (2D DEM DAC) is proposed having less design complexity compared to the conventional 2D DEM DAC. A novel unit element selection algorithm is presented in order to alleviate the need for consecutive elements selection that is mandatory in the conventional 2D DEM DAC. The flexibility of this algorithm leads to the introduction of a generalized multidimensional DEM DAC applicable to any resolutions. The multidimensional structure mitigates intersegment mismatch error and improves the spurious‐free dynamic range (SFDR) and intermodulation distortion (IMD). A 12‐bit 2D DEM DAC is simulated in 65‐nm CMOS process using the digital return‐to‐zero (DRZ) technique with 1.2 V of supply voltage and power dissipation of 26 mW. The simulation results show 63.4‐ and 60.71‐dB SFDR at near DC and Nyquist frequency, respectively, and <?61‐dB IMD with 1.25‐GHz sampling frequency.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

A practical sensorless commutation method based on virtual neutral voltage for brushless DC motor

This paper presents a low‐cost and highly practical sensorless control method for brushless DC (BLDC) motor drives. The developed methodology can generate an accurate commutation signal for the BLDC motor by sensing the back electromotive force zero‐crossing point through the virtual neutral voltage of the motor. Since commutation control is critical for the BLDC motor control, a voltage‐controlled phase shifter comprising a hysteresis comparator and voltage‐controlled resistor is proposed in order to perform phase compensation at different speeds and prevent rapid output oscillations due to noise or high‐frequency ripples in the virtual neutral voltage. Finally, several experiments have been performed on a prototype motor to verify the theoretical analysis and demonstrate the practicality and reliability of the proposed sensorless drive method. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis and effective controller design for the cascaded H‐bridge multilevel APF with adaptive signal processing algorithms

The cascaded H‐bridge (CHB) multilevel inverter is being recognized as the most suitable topology for high‐power medium‐voltage power quality conditioning applications. This paper presents mathematical modeling and effective controller design methodology for the CHB‐based active power filters (APFs), which achieves dynamic reactive power and harmonic compensation. The most crucial problems in CHB‐APF control are the simultaneous requirements of both accurate harmonic current compensation and the dc‐link voltage stabilization among the H‐bridges, which is the prerequisite for the stable operation of CHB‐APF. To achieve dc‐link stabilization, a novel voltage balancing algorithm is proposed by splitting the dc‐link voltage control task into two parts, namely, the average voltage control and the voltage balancing control, where the sine and cosine functions of the phase angle of the fundamental component of the grid voltage are used, respectively. To ensure accurate phase tracking, a novel phase‐locked loop (PLL) is proposed by using the adaptive linear neural network (ADALINE), where the grid voltage background distortion is also taken into account. The superior performance of the ADALINE‐PLL is validated by comparison with the existing PLLs in literatures. Furthermore, the proportional‐resonant (PR) controller is used for the reference current tracking. A separate ADALINE algorithm is applied for reference current generation (RCG) for the CHB‐APF. The excellent performance of the ADALINE‐based RCG scheme is verified by comparison with the existing RCG schemes, namely, the low‐pass filter approach and the single‐phase p ? qmethod. The experimental results on the three modules CHB‐APF are presented, which verifies the effectiveness of the proposed control algorithms. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

Compensation method of phase‐locked loop under unbalanced grid condition based on harmonic linearization

The voltage source converter (VSC) is often faced with unbalanced grid conditions that will degrade its performance because of the distorted current with a large amount of harmonics. One of the main parts of current distortion is the third‐order harmonics caused by the negative‐sequence voltage component at the fundamental frequency. The distorted output of the synchronous reference frame phase‐locked loop (SRF‐PLL) due to the unbalanced grid voltage is the main reason for the existence of the harmonics. This paper analyzes the mechanism of the generation of harmonics currents and proposes a compensation method for the PLL in VSCs based on the harmonic linearization method without changing the structure of SRF‐PLL. The proposed PLL can work properly under unbalanced grid conditions and has a good dynamic response. The third‐order current harmonics are reduced significantly by using the proposed PLL instead of the conventional SRF‐PLL without changing the current control strategy of VSC. The compensation method is verified by cycle‐by‐cycle circuit simulations and controller hardware‐in‐the‐loop experiments.     

Optimum design of high power and high efficiency mm‐wave fundamental oscillators

A systematic method to design high power and high efficiency mm‐wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77‐GHz two‐stage (differential) VCO is designed in a 65‐nm CMOS process. Careful electromagnetic and circuit simulations demonstrate that the designed VCO has 2‐GHz tuning range, maximum output power of 10.5 dBm and maximum DC to RF efficiency of 24.1%. The designed VCO shows 54.8% and 108.7% improvement in terms of maximum output power and efficiency compared with a conventional cross‐coupled VCO with the same tuning range.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Wide‐band divide‐by‐2 injection‐locked frequency divider using MOSFET mixers DC‐biased in subthreshold region

A novel wide locking range divide‐by‐2 injection‐locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18‐µm 1P6M CMOS process. The divide‐by‐2 ILFD is based on a cross‐coupled voltage‐controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain–source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide‐by‐2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56 mW. The die area is 0.839 × 0.566 mm². Copyright © 2015 John Wiley & Sons, Ltd.     

Design and simulation of novel amplifier‐based mixer for ISM band wireless applications

This letter describes a low‐voltage low‐power (LV‐LP) 2.4‐GHz mixer for Industrial, Scientific and Medical (ISM) band wireless applications. The approach is based on a two‐stage amplifier, and the Gilbert switch stage is inserted between the two amplifier stages. The proposed amplifier‐based mixer delivers a remarkable conversion gain of 13 dB with a local oscillator (LO) power of 7 dBm, while consuming only 1.05‐mW DC power from a 0.8‐V supply voltage. The input‐referred third‐order intercept point (IIP3) of the mixer is 3.82 dBm, and the chip area is only 0.429 mm². The results indicate that this mixer is suitable for the low‐voltage low‐power applications. Copyright © 2014 John Wiley & Sons, Ltd.     

Phase locked loop system for FACTS

This research addresses the special requirements of phase locked loops (PLLs) for a typical application with FACTS elements. A new PLL system that uses adaptation algorithms is developed with the aim of improving speed of responses, robustness to AC voltage depressions, and harmonic rejection. The adaptive PLL consists of the three control units that individually control frequency, phase angle, and voltage magnitude. The voltage controller output is used to compensate for reduced gain caused by the AC voltage magnitude depressions. The output phase angle and its derivative, the frequency signal, are controlled in two independent control systems in order to enable elimination of frequency and phase error without compromising transient responses. The simulation results are compared with a PLL available with the PSB MATLAB block-set and noticeable improvements are demonstrated. In particular, settling time and overshooting are significantly lower with conditions of reduced AC voltage magnitude.     

A new high‐frequency voltage injection method for sensorless drive of permanent‐magnet synchronous motors with pole saliency

This paper proposes a new sensorless vector control method for salient‐pole permanent‐magnet synchronous motors. In regard to rotor phase estimation, the sensorless vector control method is characterized by a new high‐frequency voltage injection method distinguished from the conventional ones by a unique ellipse shape of the spatial rotation, and by a new PLL method whose input is a high‐frequency current autocorrelated signal. The new vector control method established by two innovative technologies can have the following high‐performance and attractive features: (1) it can allow 250% rated torque at standstill; (2) it can operate from zero to the rated speed under the rated motoring or regenerating load; (3) it accepts instant injection of the rated load even for zero‐speed control; (4) it accommodates a load with huge moment of inertia; (5) phase estimation is very robust against inverter dead time; (6) the computational load for estimating rotor phase is very small, would be the smallest among the methods with comparable performance. This paper presents the new vector control method by focusing on two innovative technologies from its principles to design rules. Usefulness of the new vector control method is verified through extensive experiments. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 164(4): 62–77, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20632     

Voltage mode and current mode Tow Thomas bi‐quadratic filters using inverting CCII

A voltage mode Tow Thomas bi‐quadratic filter using the inverting second‐generation current conveyor (ICCII) is given. The filter has high input impedance, employs two grounded capacitors, and has independent control on Q, independent control on the band‐pass and low‐pass response gain. Three alternative current mode filters are generated from the voltage mode circuit. The three circuits have zero input impedance, employ grounded capacitors and have independent control on Q. Two of the circuits have also all resistors grounded and the other uses only ICCII?and has only one floating resistor. Copyright © 2007 John Wiley & Sons, Ltd.     

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

Voltage-controlled oscillator (VCO) is the most basic component required for all wireless and communication systems. In this article, a four-stage differential ring VCO with two control voltages for wide tuning range is proposed. This VCO uses the dual-delay loop technique for high operation frequency. Also, a low-V_T NMOS transistor is used in series with pull down network of the proposed VCO delay cell to achieve low frequencies. Prelayout simulation of the proposed VCO is performed in 65-nm TSMC CMOS technology in Cadence software under 1.2-V supply voltage. The tuning range of the proposed VCO varies from 1 MHz to 13.8 GHz and has been improved by 19.77% compared to other works. The power consumption of this low power VCO is between 29.3 μW to 1.715 mW. The phase noise of the proposed circuit is −82.3 dBc/Hz at 1 MHz offset frequency and −106.9 dBc/Hz at 10 MHz offset frequency from 5.161 GHz center frequency, while its area is 102.457 μm² . This design demonstrates other benefits in low power consumption and area compared with other ring oscillators.     

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output‐capacitorless quasi‐digital complementary metal‐oxide‐semiconductor (CMOS) low‐dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade‐off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post‐simulated in HSPICE in a 0.18 µm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on‐chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.