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1.
为分析Hash函数新标准SHA-3算法的安全性,从算法统计性能和轮函数Keccak-f的对称性两个方面对其进行测试。测试结果表明,SHA-3算法雪崩效应良好,平均变化比特数和平均变化概率都非常接近理想值且方差比较小,具有较高的稳定性和较低的碰撞程度; Keccak-f中添加常数的变换会严重扰乱轮函数的对称性,利用轮函数对称性对SHA-3进行内部差分攻击只适用于轮数较少的情况。  相似文献   

2.
针对当前哈希函数算法标准和应用需求不同的现状,以及同一系统对安全性可能有着不同的要求,采用可重构的设计思想,在对SHA-1、SHA-256、SHA-512三种哈希函数的不同特征进行深入分析的基础上,总结归纳出统一的处理模型。根据不同的要求,每一种SHA(SHA-1、SHA-256、SHA-512)系列哈希函数都可以单独灵活地执行。使用流水线,并在关键路径进行加法器的优化,提高了算法的吞吐率。并且使用效能比的概念,与M3服务器对比,可重构平台的效能比比通用服务器高很多。  相似文献   

3.
数字签名算法MD5和SHA-1的比较及其AVR优化实现   总被引:4,自引:0,他引:4  
MD5和SHA-1是目前使用比较广泛的散列(Hash)函数,也是在消息认证和数字签名中普遍使用的两种加密算法。本文基于AVR高速嵌入式单片机,实现了MD5和SHA-1两种加密算法的比较,并对算法进行了汇编语言的优化和改进。根据实验结果,对两种算法的优缺点进行了比较和分析。  相似文献   

4.
该文提出了基于分组密码算法Rijindael的安全Hash函数。此Hash函数基于分组长度和密钥长度均为256比特的分组密码算法Rijindael-(256,256),其输出长度为256比特。并且该文证明了此Hash算法抵抗碰撞及作为单向函数的安全性。  相似文献   

5.
随着计算机和互联网络技术的迅速发展,电子数据鉴定的结论成为具有证据力的法定证据之一,文中介绍了电子取证中基于SHA-256算法的磁盘复制审计系统的设计与实现,在分析SHA-256算法的基础上,利用FPGA芯片实现了基于SHA-256算法的磁盘复制审计系统,提出了实现磁盘复制和生成SHA-256哈希值一种电路设计方案;利用SHA-256算法对DMA传输方式中的CRC校验码进行计算得到磁盘数据摘要,从而保证了采集数据的一致性,并且整个复制过程必须是可审计的;最后讨论了基于A1tera公司生产的StratixⅡ系列FPGA的实现结果。  相似文献   

6.
一类SHA-x改进杂凑算法的设计及分析   总被引:1,自引:0,他引:1       下载免费PDF全文
在SHA-1和SHA-2标准算法的基础上,提出一类SHA-x改进杂凑算法的设计。该算法重新设计了杂凑函数Hash值的生成方法,将输出消息摘要的长度从SHA-1的160bit提高到192bit,同时保留了SHA-1模2^32加法的计算特性,以保证整个算法的加密速度。安全性分析表明,新设计的杂凑算法在不过分减慢加密速度的前提下,具有较SHA-1更好的抗攻击能力。  相似文献   

7.
胡云山  申意  曾光  韩文报 《计算机科学》2016,43(8):123-127, 147
充分条件的求解是模差分攻击的重要步骤之一。将充分条件的求解转化为F2上线性方程组的构造过程,利用线性方程组解的判定定理判断每步所求得充分条件的正确性,提出了针对SHA-1模差分攻击的充分条件自动化求解算法。文中算法做适当变形后,同样适用于MD5、SHA-0等与SHA-1结构相似的Hash函数充分条件的自动化求解。  相似文献   

8.
为了找出一种适合多核密码处理器的SHA-2算法高速实现方式,提高SHA-2算法在多核密码处理器上的执行速度。首先研究SHA-256、SHA-512算法在密码处理器上的实现方式,并研究多核密码处理器的结构特点与数据传输方式,分析SHA-2算法在多核上的高速实现原理。然后对SHA-2算法进行任务划分,提出SHA-2在多核密码处理器上的调度与映射算法并使用软件实现调度算法。在ASIC上的仿真验证结果表明,经优化后的SHA-2算法在多核上并行执行吞吐率有了较大提升,满足性能上的需求。  相似文献   

9.
DRM系统的SHA256算法设计及FPGA实现   总被引:1,自引:1,他引:1  
介绍了一种适于DRM系统的SHA-256算法和HMAC算法,给出了在FPGA上实现SHA256算法和HMAC算法的一种电路设计方案,并对算法的硬件实现部分进行了优化设计,给出了基于Altera公司的StratixⅡ系列的FPGA的实现结果。  相似文献   

10.
对SHA-1算法的完备度、雪崩效应度、严格雪崩效应及抗碰撞性进行了逐拍统计分析。针对目前密码学界所揭示出的SHA-1设计缺陷,主要以增强SHA-1算法的非线性扩散特性及抗碰撞性为目标,对其进行改进。改进算法在混合函数中逆序使用改进后的扩展码字序列,并在算法首轮的混合函数中引入整数帐篷映射,加速了差分扩散,改变了原来固定的链接变量传递方式,修正了算法内部结构的设计缺陷。测试与分析结果表明,改进算法提高了非线性扩散程度,增强了算法的安全性。  相似文献   

11.
Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs. As several 64-bit adders are needed in SHA-512 hash value computation, new architectures proposed in this paper implement modulo-64 addition as modulo-32, modulo-16 and modulo-8 additions with a view to reduce the chip area. Hash function SHA-512 is implemented in different FPGA families of ALTERA to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to guide a designer to select the most suitable FPGA for an application. In addition, a common architecture is designed for implementing SHA-256 and SHA-512 algorithms.  相似文献   

12.
At the Cryptographic Hash Workshop hosted by NIST in 2005, Lee et al. proposed the DHA-256 (Double Hash Algorithm-256) hash function. The design of DHA-256 builds upon the design of SHA-256, but introduces additional strengthening features such as optimizing the message expansion and step function against local collision attacks. Previously, DHA-256 was analyzed by J. Zhong and X. Lai, who presented a preimage attack on 35 steps of the compression function with complexity 2239.6. In addition, the IAIK Krypto Group provided evidence that there exists a 9-step local collision for the DHA-256 compression function with probability higher than previously predicted. In this paper, we analyze DHA-256 in the context of higher order differential attacks. In particular, we provide a practical distinguisher for 42 out of 64 steps and give an example of a colliding quartet to validate our results.  相似文献   

13.
This paper proposes a color image encryption scheme using one-time keys based on crossover operator, chaos and the Secure Hash Algorithm(SHA-2). The (SHA-2) is employed to generate a 256-bit hash value from both the plain-image and the secret hash keys to make the key stream change in each encryption process. The SHA-2 value is employed to generate three initial values of the chaotic system. The permutation-diffusion process is based on the crossover operator and XOR operator, respectively. Experimental results and security analysis show that the scheme can achieve good encryption result through only one round encryption process, the key space is large enough to resist against common attacks,so the scheme is reliable to be applied in image encryption and secure communication.  相似文献   

14.
Hash functions are special cryptographic algorithms, which are applied wherever message integrity and authentication are critical. Implementations of these functions are cryptographic primitives widely used in common cryptographic schemes and security protocols such as Internet Protocol Security (IPSec) and Virtual Private Network (VPN). In this paper, a novel FPGA implementation of the Secure Hash Algorithm 1 (SHA-1) is proposed. The proposed architecture exploits the benefits of pipeline and re-timing of execution through pre-computation of intermediate temporal values. Pipeline allows division of the calculation of the hash value in four discreet stages, corresponding to the four required rounds of the algorithm. Re-timing is based on the decomposition of the SHA-1 expression to separate information dependencies and independencies. This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values. Exploiting the information dependencies, the fundamental operational block of SHA-1 is modified so that maximum operation frequency is increased by 30% approximately with negligible area penalty compared to other academic and commercial implementations. The proposed SHA-1 hash function was prototyped and verified using a XILINX FPGA device. The implementation’s characteristics are compared to alternative implementations proposed by the academia and the industry, which are available in the international IP market. The proposed implementation achieved a throughput that exceeded 2,5 Gbps, which is the highest among all similar IP cores for the targeted XILINX technology.  相似文献   

15.
FPGA上SHA-1算法的流水线结构实现   总被引:1,自引:0,他引:1  
哈希算法SHA-1算法广泛地应用于电子商务、商用加密软件等信息安全领域。通过对SHA-1算法的深入分析,提出了流水线结构的硬件实现方案。通过缩短关键路径,使用片内RAM代替LE寄存器实现流水线中间变量的数据传递,有效地提高了工作频率和单位SHA-1算法的计算速度。这种硬件结构在Altera系列芯片上的实现性能是Altcra商用SHA-1算法IP核的3倍以上。  相似文献   

16.
Hash算法I3工AKE是新一代安全Hash标准SHA-3全球公开征集过程中进入最后一轮的5个候选者之一。 给出一种基于Matlab的带有图形界面GUI的BLAKE程序的设计与实现过程。本程序可用于实际的BLAKE Hash 值的运算,最重要的是为BLAKE的教学与实验提供了更方便直观的工具。  相似文献   

17.
Hash算法的快速发展导致了两个问题,一个是旧算法与新算法在应用于产品时更新换代的问题,另一个是基于应用环境的安全性选择不同算法时的复用问题。为解决这两个问题,实现了SHA-1/SHA-256/SM3算法的IP复用电路,电路采用循环展开方式,并加入流水线的设计,在支持多种算法的同时,还具有小面积高性能的优势。首先,基于Xilinx Virtex-6FPGA对电路设计进行性能分析,电路共占用776Slice单元,最大吞吐率可以达到0.964Gbps。然后,采用SMIC 0.13μm CMOS工艺实现了该设计,最后电路的面积是30.6k门,比单独实现三种算法的电路面积总和减小了41.7%,工作频率是177.62 MHz,最大吞吐率达到1.34Gbps。  相似文献   

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