基于簇内能耗最优的设备到设备缓存通信内容共享算法

针对设备到设备（D2D）缓存通信中,终端设备电池容量有限且设备之间数据传输能耗过大导致文件卸载率下降的问题,提出一种簇内节点能耗最优的缓存通信内容共享算法（CCSA）。首先,鉴于用户终端的随机分布特性,将网络中的用户节点建模为泊松簇过程,基于节点设备能量、通信距离建立卸载模型,设计自适应簇首选择权值公式;其次,遍历节点的能量与距离加权和并采用贪婪算法局部最优原则选取簇首节点,从而对用户节点通信距离进行优化,确保用户能耗最低以延长其生存周期,同时提高系统的卸载率。实验结果表明,与成簇随机选簇首（Random）、非成簇的能耗优化（EC）算法相比,所提算法在网络能耗最优时,系统生存周期延长了约60个百分点、72个百分点。CCSA能够提高卸载率且降低系统的卸载能耗。     

基于引力搜索算法的异构无线传感器网络路由分簇算法

针对异构无线传感器网络簇头节点能耗大、网络寿命较低等问题,提出一种路由分簇算法.以均衡簇头节点的能耗为目标,采用引力搜索算法对网络簇头的通信链路进行规划,从而降低簇头节点间通信的负载能耗.为同时兼顾普通节点和簇头节点的工作时间,根据普通节点与高能节点携带能量的差异和簇头节点的负载情况进行分簇.实验结果表明,所提出的路由分簇算法相对于目前优化性能较好的粒子群算法(PSO)、遗传算法(GA)和最小距离聚类法(LDC),在不同检测环境、不同的节点布撒比例下,能够更好地均衡节点能耗,从而获得更长的网络寿命.     

无线传感器网络最小能量簇群构造策略

尽可能延长无线传感器网络（WSNs）的生命周期是设计和部署网络所面临的最大挑战之一。由于节点配备的能量有限，采用分簇方式组织节点可以极大地降低节点与Sink节点通信的能耗。簇群成员节点和簇头的通信方式与簇群的拓扑结构决定整个簇群的能量消耗速度。文中分析了簇群节点采用Multi-hop通信方式时，节点通过中继节点与簇头通信时能量消耗的模型，然后在选择链路的最优跳数的基础上，提出建立最小能量中继链路的方法，实现通信能耗的最小化。对WSNs的设计和实施具有一定的指导意义。     

基于簇头预测的无线传感器网络节能算法

针对无线传感器网络寿命受节点能量制约的问题,提出基于簇头预测的节能算法。分析节点接收、发送和处理数据所需能耗与通信中数据包长度的近似线性关系,给出节能算法的能耗模型。以已有融合数据为基础,簇头利用灰色预测算法求出该簇的数据,降低簇头与非簇头节点的通信频率,使簇头以较低能耗延长其轮回周期。仿真结果表明,该算法能有效降低节点死亡速度,延长网络寿命。     

三维片上网络拓扑结构研究综述

三维片上网络(three-dimensional network on chip,3D No C)是在三维集成电路(three-dimensional integrated circuit,3D IC)、片上系统(system on chip,So C)和二维片上网络(two-dimensional network on chip,2D No C)的基础上发展起来的,主要解决高集成度芯片通信瓶颈等问题,已引起国内外学术界和产业界的高度重视。3D No C拓扑结构体现了通信节点在芯片中的布局与连接,对三维芯片性能起决定性作用。简介了2D No C、2D No C到3D No C的演变、3D No C的优点与存在的问题以及3D No C解决的关键技术问题,分析了3D No C总体发展状况。三维拓扑结构是3D No C设计中的关键问题之一,重点研究了3D No C拓扑结构的分类方法,从通信角度将3D No C拓扑结构分成9大类,分类论述了3D No C拓扑结构,并分析比较了现有63种拓扑结构各自的特点,最后指出了3D No C拓扑结构的未来研究方向。     

改进的LEACH协议在井下通信系统中的应用

无线传感器网络由能量受限的节点组成,通过部署这些节点以便收集特定监测区域内的有用信息.基于层次的LEACH协议通过将节点分簇以实现数据融合.随机选择的簇头节点接收到本簇成员的数据后进行融合处理,将结果传输到汇聚节点.避免每个节点都与远距离的汇聚节点直接通信,从而节约能耗.将无线传感器网络应用于井下通信系统,能够提高通信的安全性.LEACH的分簇结构与矿井内分坑道工作的情况相类似,把每个坑道作为一个簇,将多数传感器节点安置在坑道内的固定位置,少量节点随矿工位置移动,再将这些节点采集的数据传输至簇头节点.本文主要针对井下通信系统的特点对现有的LEACH协议进行改进,优化了簇头节点的选举方法,并允许部分节点采用多跳方式与汇聚节点通信,使其更符合矿井结构的要求,从而节约了能耗,并且有效地延长了网络的生存时间.     

一种能耗均衡的无线传感器网络分簇算法

以无线传感器网络中的LEACH和HEED分簇算法为背景,提出一种基于能耗均衡的自适应网络分簇算法EBACA。算法的主要特点是传感器节点根据自身状态信息自主竞争簇头,簇头选择标准考虑了随机概率与节点剩余能量结合,并引入了节点能量预测和能量阈值;为均衡各个节点的能耗,通过重新规划时间片来调节节点的工作频率;为减少簇头的能量开销,簇头之间通过多跳方式将各个簇内收集到的数据发送给特定簇首节点,并由此簇首节点将整个网络收集的数据发送给基站。设计的目标是均衡网络能耗,进而最大化网络寿命。分析和仿真结果表明,相对于几种重要的分簇算法,如LEACH和HEED,EBACA在平衡节点能量消耗和延长网络寿命方面具有更优越的性能。     

一种基于簇首生成树的传感器网络分簇路由协议

针对无线传感器网络中分簇路由协议LEACH存在的不足,提出了一个以簇首最小生成树为簇间路由树的改进协议LEACH_CHMST。该协议摒弃了标准LEACH中簇首与sink采用简单单跳直接通信的策略,由处理能力相对较强的sink节点发现并生成覆盖全体簇首节点的最优路由树,并实现簇首到sink的多跳通信以节省节点通信能耗。实验仿真表明,与标准LEACH协议相比较,新的协议显著提高了网络的生存时间,节省了全网的节点能耗,特别适用于大规模无线传感器网络的应用环境。     

异构传感器网络中一种基于局部簇的分簇算法

为了降低异构传感器网络中节点间的通信代价及网络能耗,首先基于分解和组合数学原理提出了局部簇的概念,使节点的工作仅局限于一个簇内而非整个网络。然后,在局部簇内又提出了一种新的分簇算法:根据节点能量异构特征选择簇首,簇首除首轮由基站选出外,其他轮数均由前一轮中的簇首节点来确定;数据传输采用混合拓扑的网络结构,簇内同构节点可直接相互通信;引入了簇维护策略,维持簇的工作状态。仿真结果表明,基于局部簇的分簇算法明显减少了簇首的能耗,降低了整个簇的能耗。鉴于簇的局部性和独立性,显而易见新算法可以有效降低整个异构传感网络的能耗。     

一种新型能耗优化的无线传感器网络成簇算法

能量消耗一直是限制WSN广泛应用的热门问题之一,能源容量的大小对各个传感器节点产生重要的影响.针对WSN中能耗过快,以及网络区域内能量消耗不均衡而导致的网络生命周期缩短的问题,同时为了提高WSN的能量利用率,提出了一种新型能耗优化的无线传感器网络非均匀成簇算法(UCNE).该算法首先根据节点的历史能耗来竞选簇头节点,将整个网络划分为不均匀的簇群从而平衡簇内节点通信与簇间节点通信的能耗.其次设立新的能量阈值作为网络重新分簇的标准,减少了频繁分簇造成的不必要的控制消息能耗.最后为了降低簇头节点的负担,竞选副簇头节点作为中继转发节点转发主簇头加工的数据并根据权值选择向前向簇头节点传递数据.通过对比相关协议,UCNE协议在平衡网络能耗,延长网络寿命方面表现更优.     

ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs

The rapid increase in the number of cores on chips forced the designers to invent new communication methods such as Network-on-Chip (NoC) paradigm. Advances in integrated circuit fabrications even allowed three-dimensional NoC (3D-NoC) implementations. 3D-NoCs have more advantages than their 2D counterparts such as lower area, higher throughput, better performance, and less energy consumption. However, they lack the design automation algorithms. An important design problem for a given application is mapping it on a 3D-NoC topology. In this paper, we present an integer linear programming (ILP) formulation and a novel heuristic algorithm, called CastNet3D, for application mapping onto mesh-based 3D-NoCs with energy minimization being the objective. The algorithm tries to utilize vertical links for communicating nodes as much as possible. Vertical links are shorter than horizontal ones; therefore, they are faster and consume less energy. We compared CastNet3D against ILP in terms of energy consumption and execution time on several benchmarks. Our results show that CastNet3D obtains close to optimum results in much shorter time frames.

     

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.     

基于ARM和FPGA的NoC资源网络接口驱动设计与实现

将ARM处理器作为NoC系统中的一个资源节点,设计了资源网路接口,基于Linux操作系统的基础上,编写了FPGA设备的驱动程序。在典型的3×32DMesh结构的NoC系统中进行了测试,结果表明该设计实现了ARM处理器资源节点和NoC系统中其他IP核数据的高速、可靠传输。     

Optimal placement of vertical connections in 3D Network-on-Chip

Due to technological limitations, manufacturing yield of vertical connections (Through Silicon Vias, TSVs) in 3D Networks-on-Chip (NoC) decreases rapidly when the number of TSVs grows. The adoption of 3D NoC design depends on the performance and manufacturing cost of the chip. This article presents methods for allocating and placing a minimal number of vertical links and the corresponding vertical routers to achieve specified performance goals. A second optimization step allows to maximize redundancy in order to deal with failing TSVs. Globally optimal solutions are determined for the first time for meshes up to 17 × 17 nodes in size. A 64-core 3D NoC is modeled based on state-of-the-art 2D chips. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, an optimal placement with 25% of vertical connections achieved 81.3% of average network latency and 76.5% of energy delay product, compared with full layer–layer connection. The performance with 12.5% and 6.25% of vertical connections are also evaluated. Our analysis and experiment results provide a guideline for future 3D NoC design.     

基于FPGA的NoC硬件系统设计

设计了基于FPGA的片上网络系统硬件平台。系统由大容量的FPGA、存储器、高速A/D与D/A、通信接口和一个扩展的ARM9系统组成。完成了集高速数字信号处理、视频编解码和网络传输功能与一体的多核系统设计。针对典型的3×3 2D Mesh结构的NoC系统应用进行了探讨,阐述了NoC系统设计过程中的关键技术,并使用SigXplorer软件对系统的信号完整性解决方案进行了PCB的反射与串扰仿真。     

保证QoS的片上网络低能耗映射与路由方法

为解决二维mesh片上网络的服务质量和低能耗问题，提出基于最优化搜索的拓扑映射与路由方法Q-LEMR．该方法以降低芯片通信能耗为目标，在保证系统延迟与带宽的服务质量的前提下，自动将给定应用的IP核映射到片上网络结构上，并为通信踪迹定制设计确定的、非死锁的最短路径路由；同时通过加速策略使映射和路由的计算在可接受的时间范围内完成．实验结果表明，Q—LEMR较现有工作平均降低通信能耗28．8％，并满足服务质量要求．     

一种不规则2DMesh的NoC路由算法

NoC的网络拓扑结构是其研究的重要方面,在一些实际应用中,NoC系统通常集成多个不同功能、不同尺寸、不同通讯需求的组件,而规则的拓扑结构并不适应于在这种类型的NoC中应用,因此不规则Mesh网络被应用于不规则的NoC系统,为解决规则Mesh路由算法在不规则Mesh中无法保证路由连通性问题。提出一种不规则Mesh无死锁路由算法,同时此算法与其他算法相比,具有更少的虚通道和更优秀的路由路径选择。     

Mapping multiple applications onto 3D NoC-based MPSoCs supporting wireless links

Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.     

片上网络体系结构的研究与进展

片上网络(NoC)是基于多处理器技术的一种新型的计算集成形式，涉及硬件通信结构、中间件、操作系统通信服务、设计方法及工具等。NoC体系结构的设计重点是实现低功耗和高效通信/计算能力。该文介绍了4种新的NoC体系结构，并在同等约束下进行了功耗比较，2D网格结构的功耗最大、性能最差，聚合环面网络结构则最优。     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.