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1.
Minix新增系统调用的设计与实现   总被引:4,自引:1,他引:4  
在分析和研究Minix操作系统时,发现必须增加新的系统调用,本文首先介绍了增加系统调用的必要性,接着分析比较了在基于微内核设计的Minix操作系统上增加系统的调用的各种可能方案,在此基础上,详细描述了中继方案的设计与实现。本文最后给出了新增系统调用的应用。  相似文献   

2.
进程间通信作为操作系统中最重要的原语之一,提供了在多个隔离的进程之间相互通信交流的可能性.提出了一种适用于微内核操作系统的进程间通信系统,并在具体的Minix操作系统平台之上予以实现,解决了Minix系统中由于进程间通信模块的缺失而导致开发人员无法顺利移植其他平台的实用程序的问题。实验数据表明,该进程间通信系统具有高效的特点;同时由于该系统的设计原则。它保持着易扩展的特点。该系统的实现虽然是基于Minix平台,但该设计同样适用于其他微内核的系统,对其他操作系统具有借鉴意义。  相似文献   

3.
进程间通信作为操作系统中最重要的原语之一,提供了在多个隔离的进程之间相互通信交流的可能性.提出了一种适用于微内核操作系统的进程间通信系统,并在具体的Minix操作系统平台之上予以实现,解决了Minix系统中由于进程间通信模块的缺失而导致开发人员无法顺利移植其他平台的实用程序的问题。实验数据表明,该进程间通信系统具有高效的特点;同时由于该系统的设计原则,它保持着易扩展的特点。该系统的实现虽然是基于Minix平台,但该设计同样适用于其他微内核的系统,对其他操作系统具有借鉴意义。  相似文献   

4.
通用操作系统实时化主要是针对Linux、Unix系统的实时化,是实时操作系统开发的一个重要途径,以微内核结构的Unix系统Minix为基础,对其进行了整体的实时架构,主要包括中断处理和进程调度机制的实时化设计,并对设计的合理性进行了测试.  相似文献   

5.
为监控用户加载的驱动程序在语义方面的恶意行为,将监控服务器(MS)引入微内核操作系统Minix.监控服务器执行对消息流的截取和分析,依靠事先注册的策略数据和策略函数,判断驱动程序是否存在语义上的恶意.实验结果证明,MS行之有效,并且内核态实现方式不会对系统性能造成较大的影响.  相似文献   

6.
基于Kylin操作系统的TPC-W性能测试研究   总被引:3,自引:0,他引:3  
易伟  阳国贵 《微计算机信息》2006,22(31):310-312
Kylin是我国国产服务器操作系统,为了评测Kylin操作系统对数据库的支持和提升操作系统性能,根据TPC-W测试基准的要求,设计并实现了一个基于Kylin操作系统的TPC-W的性能测试系统,对其体系结构提出设计方案,并具体阐述了整个实现的过程。最后在Kylin操作系统和Fedora4下进行了TPC-W的对比测试,找到影响Kylin操作系统数据库性能的主要因素。  相似文献   

7.
《计算机》1999,(21)
Linux操作系统于1991年诞生于芬兰。当时的Linus Torvalds还是赫尔辛基大学的学生。他的目的是做一个代替Minix操作系统,可用于基于Intel PC机的类似UNIX的操作系统。在Linus Torvalds和全世界数以百计的程序员的共同努力下,Linux已经成为一个可以运行在Intel,Motorola MC68K以及DEC的Alpha平台下的多用户,多任务的操作系  相似文献   

8.
一、问题大家都知道,Linux是T.Linus在学习Minix时依据自己的思路去开发自己的操作系统时的作品。一开始并没打算要建造一套完整的操作系统内核,他关注的纯粹只是为了一种需要,就是阅读网络新闻组。只是在其将自己的作品发表在Minix新闻组里,才最终使这个完全个人化的创意得以脱胎换骨成为一个如今的电脑行业顶级“传奇”。Linux的影响不仅仅是它是一个成功的操作系统,是值得象IBM这样的“兰色巨人”都要“拥抱”的系统,也不仅仅是一个源码开放、充满自由软件所代表的“自由”精神的一个系统,而且在于从表面上看一个大型复杂的操作系统可以通过互联网在千万人参与下获得成功的惊人之举,实质上是它所代表的一种新的软件工程理念和方法,至少是一种新的软件系统开发模式。  相似文献   

9.
操作系统性能是对其进行综合评测的重要指标之一。本文以多个主流Linux服务器操作系统的性能测试实践为基础,概括了对Linux操作系统进行性能测试和对比评测的测试策略和性能测试工具的选择原则,并对主要性能测试工具和关键性能指标进行了说明。  相似文献   

10.
TPC-C是一种旨在衡量联机事务处理(OLTP)系统性能与可伸缩性的行业标准基准测试项目,它被全球主流计算机硬件厂商,数据库厂商公认为性能评价标准。目前开源的事务处理性能测试软件,很少有严格符合TPC-C标准的开源测试软件,难以对测试系统进行公正的性能评价。Kylin是我国国产服务器操作系统,为了评估Kylin操作系统的性能,避免测试软件造成的性能瓶颈,本文基于Kylin操作系统,通过整合中间件BEATuxedo,应用服务器Apache和数据库管理系统Oracle,设计并实现了一个TPC-C测试系统。该系统严格遵循TPC-C规范,减少由于测试软件的不足对测试结果的影响,为Kylin操作系统的性能调优提供了一定的参考。  相似文献   

11.
VI-attached database storage   总被引:1,自引:0,他引:1  
This work presents a Vl-attached database storage architecture to improve database transaction rates. More specifically, we examine how Vl-based interconnects can be used to improve I/O path performance between a database server and a storage subsystem. To facilitate the interaction between client applications and a Vl-aware storage system, we design and implement a software layer called DSA, that is layered between applications and VI. DSA takes advantage of specific VI features and deals with many of its shortcomings. We provide and evaluate one kernel-level and two user-level implementations of DSA. These implementations trade transparency and generality for performance at different degrees and, unlike research prototypes, are designed to be suitable for real-world deployment. We have also investigated many design trade offs in the storage cluster. We present detailed measurements using a commercial database management system with both microbenchmarks and industrial database workloads on a mid-size, 4 CPU, and a large, 32 CPU, database server. We also compare the effectiveness of Vl-attached storage with an iSCSI configuration, and conclude that storage protocols implemented using DSA over VI have significant performance advantages. More generally, our results show that Vl-based interconnects and user-level communication can improve all aspects of the I/O path between the database system and the storage back-end. We also find that to make effective use of VI in I/O intensive environments, we need to provide substantial additional functionality than what is currently provided by VI. Finally, new storage APIs that help minimize kernel involvement in the I/O path are needed to fully exploit the benefits of Vl-based communication.  相似文献   

12.
In situ analysis has been proposed as a promising solution to glean faster insights and reduce the amount of data to storage. A critical challenge here is that the reduced dataset is typically located on a subset of the nodes and needs to be written out to storage. Data coupling in multiphysics codes also exhibits a sparse data movement pattern wherein data movement occurs among a subset of nodes. We evaluate the performance of data movement for sparse data patterns on the IBM Blue Gene/Q supercomputing system “Mira” and identify performance bottlenecks. We propose a multipath data movement algorithm for sparse data patterns based on an adaptation of a maximum flow algorithm together with breadth-first search that fully exploits all the underlying data paths and I/O nodes to improve data movement. We demonstrate the efficacy of our solutions through a set of microbenchmarks and application benchmarks on Mira scaling up to 131,072 compute cores. The results show that our approach achieves up to 5 × improvement in achievable throughput compared with the default mechanisms.  相似文献   

13.
In a distributed shared memory (DSM) multiprocessor, the processors cooperate in solving a parallel application by accessing the shared memory. The latency of a memory access depends on several factors, including the distance to the nearest valid data copy, data sharing conditions, and traffic of other processors. To provide a better understanding of DSM performance and to support application tuning and compiler development for DSM systems, this paper extends microbenchmarking techniques to characterize the important aspects of a DSM system. We present an experiment-based methodology for characterizing the memory, communication, scheduling, and synchronization performance, and apply it to the Convex SPP1000. We present carefully designed microbenchmarks to characterize the performance of the local and remote memory, producer-consumer communication involving two or more processors, and the effects on performance when multiple processors contend for utilization of the distributed memory and the interconnection network  相似文献   

14.
Assessing the performance of emerging high-speed networks is difficult. Our communication microbenchmark evaluates design changes in a communications system. Our microbenchmark generates a graphical signature from which we extract communication performance parameters for the hardware-software tandem. We use the LogP conceptual model for communication systems. (LogP stands for the parameters latency, overhead, gap, and processors). We study three important platforms that represent diverse points in the network interface design space: the Intel Paragon, Meiko CS-2, and a cluster of Sparcstation-20s connected by Myrinet switches using LANai SBus cards. Our study views each machine as a gray box supporting Active Messages and conforming to the LogP framework. We devise a simple set of communication microbenchmarks and measure the performance on each platform to obtain the LogP parameters  相似文献   

15.
Today's distributed and high-performance applications require high computational power and high communication performance. Recently, the computational power of commodity PCs has doubled about every 18 months. At the same time, network interconnects that provide very low latency and very high bandwidth are also emerging. This is a promising trend in building high-performance computing environments by clustering - combining the computational power of commodity PCs with the communication performance of high-speed network interconnects. There are several network interconnects that provide low latency and high bandwidth. Traditionally, researchers have used simple microbenchmarks, such as latency and bandwidth tests, to characterize a network interconnects communication performance. Later, they proposed more sophisticated models such as LogP. However, these tests and models focus on general parallel computing systems and do not address many features present in these emerging commercial interconnects. Another way to evaluate different network interconnects is to use real-world applications. However, real applications usually run on top of a middleware layer such as the message passing interface (MPI). Our results show that to gain more insight into the performance characteristics of these interconnects, it is important to go beyond simple tests such as those for latency and bandwidth. In future, we plan to expand our microbenchmark suite to include more tests and more interconnects.  相似文献   

16.
The increasing attention on deep learning has tremendously spurred the design of intelligence processing hardware. The variety of emerging intelligence processors requires standard benchmarks for fair comparison and system optimization (in both software and hardware). However, existing benchmarks are unsuitable for benchmarking intelligence processors due to their non-diversity and nonrepresentativeness. Also, the lack of a standard benchmarking methodology further exacerbates this problem. In this paper, we propose BenchIP, a benchmark suite and benchmarking methodology for intelligence processors. The benchmark suite in BenchIP consists of two sets of benchmarks: microbenchmarks and macrobenchmarks. The microbenchmarks consist of single-layer networks. They are mainly designed for bottleneck analysis and system optimization. The macrobenchmarks contain state-of-the-art industrial networks, so as to offer a realistic comparison of different platforms. We also propose a standard benchmarking methodology built upon an industrial software stack and evaluation metrics that comprehensively reflect various characteristics of the evaluated intelligence processors. BenchIP is utilized for evaluating various hardware platforms, including CPUs, GPUs, and accelerators. BenchIP will be open-sourced soon.  相似文献   

17.
In order to achieve an optimum performance of a given application on a given computer platform, a program developer or compiler must be aware of computer architecture parameters, including those related to branch predictors. Although dynamic branch predictors are designed with the aim of automatically adapting to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance. Yet, exact predictor implementations are seldom made public, even though processor manuals provide valuable optimization tips. This paper presents an experimental flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on‐chip performance monitoring registers. Such knowledge can be used either for manual code optimization or for design of new, more architecture‐aware compilers. Three examples illustrate how insight into exact branch predictor organization can be directly applied to code optimization. The proposed experimental flow is illustrated with microbenchmarks tuned for Intel Pentium III and Pentium 4 processors, although they can easily be adapted for other architectures. The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation. Copyright © 2004 John Wiley & Sons, Ltd.  相似文献   

18.
When developers need to improve the performance of their applications, they usually use one of the many existing profilers. These profilers generally capture a profile that represents the execution time spent in each method. The developer can thus focus her optimization efforts on the methods that consume the most time. In this paper we argue that this type of profile is insufficient for tuning interactive applications. Interactive applications respond to user events, such as mouse clicks and key presses. The perceived performance of interactive applications is directly related to the response time of the program.In this paper we present listener latency profiling, a profiling approach with two distinctive characteristics. First, we call it latency profiling because it helps developers to find long latency operations. Second, we call it listener profiling because it abstracts away from method-level profiles to compute the latency of the various listeners. This allows a developer to reason about performance with respect to listeners, also called observers, the high level abstraction at the core of any interactive Java application.We present our listener latency profiling approach, describe LiLa, our implementation, validate it on a set of microbenchmarks, and evaluate it on a complex real-world interactive application. We then perform case studies where we use LiLa to tune the perceptible performance of two interactive applications, and we show that LiLa is able to pinpoint performance problems even if their causes are embedded in the largest interactive Java application we are aware of.  相似文献   

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