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1.
For different delay models,the concept of sensitization can be very different.Traditonal concepts of sensitization cannot precisely describe circuit behavior when the input vectors change very fast.Using Boolean process aporoach,this paper presents a new definition of sensitization for arbitrary input waveforms.By this new concept it is found that if the inputs of a combinational circuit can change at any time,and each gate‘s delay varies within an interval (bounded gate delay model),then every path,which is not necessarily a single topological path,is sensitizable.From the experimental results it can be seen that,all nonsensitizable paths for traditional concepts actually can propagate transitions along them for some input waveforms.However,specified time between input transitions(STBIT) and minimum permissible pulse width(ε)are two major factors to make some paths non-sensitizable.  相似文献   

2.
In this paper, a new technique called test derivation is presented,aiming at the promotion of the random testing efficiency for combinational circuits,Combined with a fault simulator based on critical path tracing method,we introduce the concept of seed test derivation and attempt to generate a group of new tests from the seed test by means of critical path transition.The neccessary conditions and efficient algorithms are proposed to guarantee the usefulness of the newly derived tests and the correctness of the critical path transitions.Also,examples are given to demonstrate the effectiveness of the technique.  相似文献   

3.
IDDT: Fundamentals and Test Generation   总被引:5,自引:0,他引:5       下载免费PDF全文
It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.  相似文献   

4.
Detection of path delay faults requires two-pattern tests.BIST technique provides a low-cost test solution.This paper proposes an approach to designing a cost-effective deterministic test pattern generator(IPG) for path delay testing.Given a set of pre-generated test-pattern generator(TPG) for path delay testing.Given a set of pre-generated test-pairs with pre-determined fault coverage,a deterministic TPG is synthesized to apply the given test-pair set in a limited test time.To achieve this objective,configuable linear feedback shift register(LFSR)structures are used.Techniques are developed to synthesize such a TPG.which is used to generate an unordered deterministic test-pair set.The resulting TPG is very efficient in terms of hardware size and speed performance.SImulation of academic benchmark circuits has given good results when compared to alternative solutions.  相似文献   

5.
Fault-tolerant systems have found wide applications in military,industrial and commercial areas.Most of these systems are constructed by multiple-modular redundancy or error control coding techniques,They need some fault-tolerant specific components (such as voter,switcher,encoder,or decoder) to implement error-detecting or error-correcting functions.However, the problem of error detection location or correction for fault-tolerance specific components them-selves has not been solved properly so far.Thus ,the dependability of a whole fault-tolerant system will be greatly affected.This paper presents a theory of robust fault-masking digital circuits for characterizing fault-tolerant systems with the ability of concurrent error location and a new scheme of dual-modular redundant systems with partially robust fault-masking prperty.A Basic robust fault-masking circuit is composed of a basic functional circuit and an error-locting corrector,Such a circuit not only has the ability of concurrent error correction,but also has the ability of concurrent error location.According to this circuit model ,for a partially robust fault-making dual-modular redundant system,two redundant modules based on alternating-complementary logic consist of the basic functional circuit.An error-correction specific circuit named as alternating-complementary corrector is used as the error-locating corrector.The performance(such as hardware complexity, time delay) of the scheme is analyzed.  相似文献   

6.
A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.  相似文献   

7.
In this paper,a simulation system of pseudo-random testing is described first to investigate thecharacteristics of pseudo-random testing.Several interesting experimental results are obtained.It isfound out that initial states of pseudo-random sequences have little effect on fault coverage.Fixedconnection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less thanthe number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as mdecreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when anLFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuitinputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using anLFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator isproposed in which m相似文献   

8.
A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes(RTDs).It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation.A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation,and the JK flip-flop also has two optional types of output structure.The design of the ternary RTD JK flip-flop is verified by simulation.The RTD literal circuit is the key design component for achieving various types of multi-valued logic(MVL) flip-flops.It can be converted into ternary D and JK flip-flops,and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships.All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations.This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.  相似文献   

9.
The input time delay is always existent in the practical systems. Analysis of the delay phenomenon in a continuous-time domain is sophisticated. It is appropriate to obtain its corresponding discrete-time model for implementation via digital computer. This paper proposes a new discretization method for calculating a sampled-data representation of nonlinear time-delayed non-affine systems. The proposed scheme provides a finite-dimensional representation for nonlinear systems with non-affine time-delayed input enabling existing nonlinear controller design techniques to be applied to them. The performance of the proposed discretization procedure is evaluated by using a nonlinear system with non-affine time-delayed input. For this nonlinear system, various time delay values are considered.  相似文献   

10.
The conventional Kalman filter is based on the assumption of non-delayed measurements. Several modifications appear to address this problem, but they are constrained by two crucial assumptions: 1) the delay is an integer multiple of the sampling interval, and 2) a stochastic model representing the relationship between delayed measurements and a sequence of possible non-delayed measurements is known. Practical problems often fail to satisfy these assumptions, leading to poor estimation accuracy and frequent track-failure. This paper introduces a new variant of the Kalman filter, which is free from the stochastic model requirement and addresses the problem of fractional delay.The proposed algorithm fixes the maximum delay(problem specific), which can be tuned by the practitioners for varying delay possibilities. A sequence of hypothetically defined intermediate instants characterizes fractional delays while maximum likelihood based delay identification could preclude the stochastic model requirement. Fractional delay realization could help in improving estimation accuracy. Moreover, precluding the need of a stochastic model could enhance the practical applicability. A comparative analysis with ordinary Kalman filter shows the high estimation accuracy of the proposed method in the presence of delay.  相似文献   

11.
基于布尔过程论的层次化延时分析方法   总被引:7,自引:0,他引:7  
芯片设计的日益复杂化和高速化对电路精确的定时特性提出了越来越高的要求。电路的延时不仅与电路的拓扑结构有关,而且还与电路的逻辑功能及输入都有密切的关系。采用Boole过程论这种统一描述数字电路的逻辑行为和时变行为的代数形式作为理论基础,提出了波形多项式偏导的概念,并用之重新定义了敏化。用偏导定义的敏化改进了解析延时模型,基于最长可敏化通路的延时建立了电路模块或子电路的延时矩阵模型,由延时矩阵模型出发提出了一种精确的电路层次化延时分析方法。最后用实验验证了文中提出的延时分析方法的有效性。  相似文献   

12.
李华伟 《集成技术》2013,2(6):54-64
先进集成电路工艺下,时延测试是数字电路测试的一项重要内容。各种时延偏差来源如小时延缺陷、工艺偏差、 串扰、电源噪声、老化效应等,影响着电路的额定时钟频率,是时延测试中需要考虑的因素。文章在介绍电路时延偏差 问题的各种来源的基础上,给出了针对不同的时延偏差问题所涉及的分析、建模、测试生成与电路设计等关键技术。进 一步介绍了中国科学院计算技术研究所近年来在考虑时延偏差的数字电路时延测试方面所做的研究工作,包括:考虑串 扰/电源噪声的时延测试、基于统计定时分析的测试通路选择、片上时延测量、超速测试、测试优化、在线时序检测等方 面。文章最后对数字电路时延测试技术的发展趋势进行了总结。  相似文献   

13.
随着特征尺寸进入纳米尺度,相邻连线之间的电容耦合对电路时序的影响越来越大,并可能使得电路在运行时失效.准确和快速地估计电路中的串扰效应影响,找到电路中潜在的串扰时延故障目标,并针对这些故障进行测试是非常必要的.文中提出了一种基于通路的考虑多串扰引起的时延效应的静态时序分析方法,该方法通过同时考虑临界通路及为其所有相关侵略线传播信号的子通路来分析多串扰耦合效应.该方法引入了新的数据结构"跳变图"来记录所有可能的信号跳变时间,能够精确地找到潜在的串扰噪声源,并在考虑串扰时延的情况下有效找到临界通路及引起其最大串扰减速效应的侵略子通路集.这种方法可以通过控制跳变图中时间槽的大小来平衡计算精度和运行时间.最后,文中介绍了在基于精确源串扰通路时延故障模型的测试技术中,该静态时序分析方法在耦合线对选择和故障敏化中的应用.针对ISCAS89电路的实验结果显示,文中提出的技术能够适应于大电路的串扰效应分析和测试,并且具有可接受的运行时间.  相似文献   

14.
基于测量的时延故障诊断   总被引:2,自引:0,他引:2  
李华伟  李忠诚  闵应骅 《计算机学报》1999,22(11):1178-1183
与时延测试相比,时延故障诊断需要更精确的故障模型。该文提出了采用精确测量的时延模型和时延故障模型。在这种模型下,利用电路通路图的原理,得到与被测电路的拓扑结构有关的一个精简测试集。测试集的大小与电路的大小保持线性增长关系;其中的每一个测试对应于一条通路的单跳变敏化向量,将测试集中的单跳变敏化向量送入被测电路,可以用测试仪测量相应通路的延时,得到电路关于此测试集的时延故障症候。该文对时延故障症候提供  相似文献   

15.
可测性设计(DFT)方法广泛应用于数字电路测试中.通过添加测试硬件,用来降低测试的复杂性。但添加测试硬件后,往往会引起电路的延时变大,从而降低电路的性能,甚至引起延时故障。针对寄存器传输级(RTL)数据通路,文献[1]提出了两种功耗限制下非扫描内建自测试(BIST)方法。跟以前的方法相比较,这两个方法取得较短的测试应用时间和较低的测试硬件开销。本文对这两个方法对电路延时的影响进行分析。实验结果表明,在保持同样的测试应用时间和测试硬件开销的前提下,电路的延时有稍微增加。  相似文献   

16.
采用一阶差分方程对时滞Lorenz混沌系统进行预处理,提出了基于DSP Builder的时滞混沌系统数字电路设计方法.此方法克服了用模拟电路设计混沌系统时,对元器件偏差及环境影响较敏感的缺陷,同时对时滞混沌系统的混沌抑制问题进行了讨论,针对系统模型描述,设计了线性控制器,并在系统离散化的基础上进行了系统数字电路设计;最...  相似文献   

17.
赵宇虹  李忠诚 《计算机学报》1997,20(10):908-917
本文提出了一种形式表示带时间参数布尔函数(Timed Boolean Functino或TBF)的新方法---带时间参数的二叉判定图(Timed Binary Decision Diagram或TBDD),并将其应用于电路时间延迟的准确计算。TBDD是传统而尔函数的符号表示---有序二叉判定图(OBDD)的扩展,可以统一地描述电路的逻辑功能和时间特征。由于采用了有效的压缩和节点共享策略,在典型的应  相似文献   

18.
提出利用瞬态电流测试(IDDT Testing)方法检测数字电路中的冗余固定故障。检测时采用双向量模式,充分考虑逻辑门的延时特性。针对两类不同的冗余固定故障,分别给出了激活故障的算法,在此基础上再对故障效应进行传播。SPICE模拟实验结果表明,该方法能有效地区分正常电路与存在冗余故障的电路,可以作为电压测试方法的一种有益的补充。  相似文献   

19.
In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL)circuit,defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits.However,less effort has been made to improve circuit delay by defect-tolerant strategies.In this paper,the factors affecting the delay of mapped circuits are analyzed,and the path-tree based defect-tolerant mapping method for the delay optimization is proposed.From the logic-domain,the terminology of the path tree is presented,and the logic circuit is first partitioned into multiple path trees.Then,the mapping areas in the physic-domain are pre-planned for (near) critical path trees.During the mapping process,the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting;(near) critical path trees are mapped with priority,while the others are mapped in a hierarchical way.Finally,an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method.Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.  相似文献   

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