基于FPGA的步进电机控制芯片设计

研究了一种以FPGA为基础的步进电机控制芯片的设计,本芯片采用Actel公司的ProASIC3系列FPGA:A3P030进行开发,采用Verilog HDL硬件描述语言进行硬件电路设计,使用Actel公司出品的Libero集成开发环境,通过C8051F060单片机,以C语言为开发语言对设计的芯片进行实际测试.     

开发FPGA应用的新设计环境

将软件设计方法引入到硬件设计中，来开发FPGA应用是一种新的设计思想。软件DKl是无需使用硬件描述语言HDL设计，由高级语言Handle-C直接设计实现FPGA应用的开发环境。     

面向FPGA芯片开发的测试方法设计与实现

相较于ASIC芯片测试而言,FPGA芯片在进行测试时往往会在难度和复杂情况上有一定的增加,本文主要针对于此设计了有关面向于FPGA芯片开发方面的测试方法,并进行详细的阐述以实现对于该芯片的检测。     

基于System Generator的FFT算法的实现

System Generator for DSP是Xilinx公司开发的基于Simulink图形环境的DSP开发工具。利用System Generator工具,即使是没有多少FPGA设计经验的设计人员也能够快速开发出高性能的FPGA来实现DSP算法。本文介绍了一种采用XILINX公司的Virtex-2 Pro系列的FPGA芯片实现FFT算法的设计流程,并利用System Generator把FFT算法映射到FPGA资源中。实验表明：该方法具有操作简单、设计灵活、效率高等优点。     

FPGA未来之路

随着FPGA的芯片密度超过10万门,FPGA的设计越来越接近于ASIC设计。为了提高开发效率,增加已有成果的可继承性,同时缩短开发周期,在FPGA设计中,己经大量使用了HDL语言(包括VHDL语言和Verilog语言),这样做可以大大降低     

通用课件开发系统UCADS的设计与实现

本文介绍了基于“工具－生成器－课件”三个技术层次结构思想的通用课件开发系统ＵＣＡＤＳ。该系统是由多项专用功能工具和实现规划、开发、执行与管理的高层系统软件所组成的集成化开发平台，它为课件开发人员提供一个良好的开发环境。其主要技术特征有：①将课件描述语言、高级程序设计语言和写作工具融为一体，使课件开发灵活方便，编程效率比传统方法提高１０倍以上。②支持多媒体和网络环境，可方便地控制录像机、语音设备、     

基于FPGA的Intel 8254的设计与实现

针对Intel 8254在某些工程应用中的局限性,提出利用FPGA和VHDL语言实现8254的设计思想;按照8254的内部逻辑结构及功能,将VHDL设计分为4个独立的功能模块,并分别介绍了各个功能模块的主要设计要点;以Altera公司的FPGA(Cyclone)系列产品为载体,在QuartusⅡ开发环境下,进行仿真和下载验证,效果良好;结果表明,利用FPGA设计并实现8254芯片功能具有可行性,同时,采用FPGA设计方法可以根据实际应用需求对芯片功能进行取舍和优化,因而具有更好的灵活性。     

基于Xilinx ISE平台的FPGA电路设计

Xilinx ISE集成综合环境是Xilinx公司的现场可编程逻辑器件数字电路开发工具集。其集成的工具可以使设计人员方便的完成CPLD/FPGA数字电路开发全过程。通过设计一个微指令控制的计算单元,描述基于ISE平台使用VHDL语言进行FPGA电路设计的原理和方法。     

基于VHDL语言的FPGA设计

采用VHDL语言在Xilinx公司的FPGA芯片上实现通用8255芯片的设计,具体介绍了基于VHDL语言的FPGA设计和优化设计的方法。     

高速数字电路的FPGA实现技巧

高速数字电路是工程设计的一个难点和重点;FPGA和EDA工具提供了实现高速数字电路的资源和技术,把高速数字电路设计与FPGA技术相结合,依靠FPGA芯片和EDA工具所提供的功能来设计高速数字电路,将大大简化高速数字电路的设计难度和工程时间;在FPGA实现高速数字电路的过程中经常遇到的3个问题:时钟偏移、同步器的亚稳态性,以及高速传输接口的处理;在深入理解亚稳态,时钟偏移的产生机理和充分利用FPGA和EDA软件的基础上,可以比较快速地解决以上问题.     

Knowledge representation framework for interactive capture and management of reflection process in product concepts development

A design process can be characterized by reflection-in-action; that is, the process consists of a series of problem solving activities and each is embodied with a problem and a solution. In this process, a designer represents a hypothetical concept on each design alternative, deploys and verifies the concept from multiple viewpoints considering other alternatives, and modifies it. An advanced integrated design environment should be based on a representation framework that embodies this process of reflection in concept development, which usually remains in the realm of the designer’s tacit knowledge. This paper proposes a knowledge representation framework for an integrated design environment, named DRIFT (Design Representation Integration Framework of Three layers), which interactively captures and manages reflection processes of generating and verifying design concepts. The core of DRIFT is a three-layered design process model of actions, operations, and argumentation. This model integrates various design tools and captures performed design activities. The action level captures the sequence of design operations. The model operation level captures the transition of design states, recording a design snapshot over design tools, which are integrated through ontology-based representation of design concepts. The argumentation level captures the process of defining problems and corresponding alternative solutions. Integration of three levels with a template of design operation extracted from Design-For-X approaches enables a proposed system to interactively and efficiently capture and manage the process of design concept development through operations over design tools. A design operation template works to limit the number of links between the three levels remaining easy to manage its semantics. This paper also demonstrates a prototype implementation of DRIFT and its application to conceptual design of a small mechatronic system with a system modeling method. The paper concludes with a discussion of some future issues.     

用Verilog HDL进行FPGA设计的一些基本方法

随着FPGA技术和自动设计工具的进步．数字电子系统设计的方法正在发生变化。越来越多的工程师开始使用硬件描述语言和高级综合工具进行设计、Verilog HDL作为一种流行的硬件描述语言．在数字系统设计特别是FPGA设计中有着广泛的应用。本文主要介绍了用Verilog HDL进行FPGA设计和优化的一些实用方法．最后还介绍了IP核复用技术在FPGA设计中的应用。     

基于嵌入式逻辑分析仪SignalTapⅡ的系统调试技术研究

首先介绍了嵌入式逻辑分析仪SignalTapⅡ的基本原理和操作流程,并结合实例详细说明了SignalTapⅡ在系统调试过程中的应用。使用SignalTapⅡ对系统进行调试,解决了器件管脚不够或不方便外挂测试工具等软硬件调试的困难,避开了电路板测试时连接器引起的信号完整性问题。实验结果表明,该方法大大减少了系统调试、验证时间,缩短了设计周期,提高了系统设计的灵活性。     

Creative connections: user, designer, context, and tools

The design symposium ‘creative connections discusses the designers’ tools in the conceptual phase. Over the past few decades, many considerations, which hitherto occured before or after conceptualizing have become an integrated part of concept development. Examples are studies of users and contexts, and expressive new materials. Also, design tools are becoming increasingly, almost exclusively, computer-based. But current computer tools lack fluency, directness, and bodily involvement of the traditional paper tools, properties which are essential in the creative activities of conceptualizing, The symposium, and its four attached bazaar papers, deal with new tools that are being developed, and old tools that are evolving, to help designers at coping with this complexity of factors. This paper is part of the 3AD design colloquium creative connections.     

Integrating a constraint-based optimization approach into the design of oil & gas structures

Currently, design optimization is widely applied in civil and mechanical engineering. Optimization strategies are used to enhance the product performance and reduce the cost, lead time and environmental impacts related to the product lifecycle. In this context, evolutionary algorithms are used for determining the optimum solution in engineering problems. The design of complex products, such as those that are engineered to order, often requires the study of subproblems. Modularization is a common practice to reduce the complexity; however, the configuration practices are difficult to be applied in engineered to order products. As a solution, the integration of the optimization tools and model-based simulations is proposed to manage the complexity. However, even when a commercial software is available to support the parameter optimization, there may exist a lack of design tools that can be integrated with the product structure of an engineered to order product. This paper describes a design optimization approach that integrates a Constraint Satisfaction Problem (CSP) tool with model-based simulations in a collaborative design context. A platform tool is developed using the .NET and MiniZinc languages. The case study is focused on the design optimization of a 700-ton steel structure. In particular, the optimization analysis considers the mechanical behavior, weight, and cost reduction.     

力驱动三维FPGA布局算法

三维FPGA布局问题的复杂度与二维情况相比成指数倍增长,布局算法需要花费大量时间,影响了FPGA物理设计效率.为了在保证布局质量的前提下缩短布局时间,提出以线长为优化目标基于力驱动的三维FPGA布局算法——3D-WFP.该算法由整体布局、坐标合法化和层划分、布局优化3个阶段组成,通过力驱动算法快速形成整体布局,为后续2个子过程提供更精确的逻辑单元位置和时延信息.提出三维空间填充曲线,根据位置和时延信息依次对逻辑单元按照三维空间填充曲线进行坐标合法化和层划分;修正了低温模拟退火进行布局优化的解空间,大大加快了低温模拟退火的收敛速度.与已有的三维FPGA布局算法比较,3D-WFP在保证运行时间和时延性能的前提下,有效地缩短了最终布局结果,缩短的总线长达7.38%.     

Design parameterization and tool integration for CAD-based mechanism optimization

This paper presents an open and integrated tool environment that enables engineers to effectively search, in a CAD solid model form, for a mechanism design with optimal kinematic and dynamic performance. In order to demonstrate the feasibility of such an environment, design parameterization that supports capturing design intents in product solid models must be available, and advanced modeling, simulation, and optimization technologies implemented in engineering software tools must be incorporated. In this paper, the design parameterization capabilities developed previously have been applied to support design optimization of engineering products, including a High Mobility Multi-purpose Wheeled Vehicle (HMMWV). In the proposed environment, Pro/ENGINEER and SolidWorks are supported for product model representation, DADS (Dynamic Analysis and Design System) is employed for dynamic simulation of mechanical systems including ground vehicles, and DOT (Design Optimization Tool) is included for a batch mode design optimization. In addition to the commercial tools, a number of software modules have been implemented to support the integration; e.g., interface modules for data retrieval, and model update modules for updating CAD and simulation models in accordance with design changes. Note that in this research, the overall finite difference method has been adopted to support design sensitivity analysis.     

DSP/BIOS在雷达目标检测系统上的应用

介绍了TI公司的实时操作系统（RTOS）内核DSP／BIOS，阐明了使用DSP／BIOS开发雷达目标检测系统的优点。先利用FPGA控制高速A／D对雷达视频数字化，然后使用DSP／BIOS内核构建多个数字信号处理线程，通过芯片支持库（CSL）配置外设资源，最后对程序进行实时分析和优化。从而大大降低了DSP系统开发的复杂度，缩短了开发周期，顺利实现了雷达目标自动检测等功能。