基于CORBA和WebLogic的电子商务系统的研究与开发

随着基于Internet技术的电子商务的普及,传统的Chent／Server二层体系结构不再适应更为复杂和灵活的大规模商业应用的需求,逐渐被三层甚至多层体系结构所代替,其中,采用应用服务器作为中间件的三层体系结构在电子商务系统中得到了较为广泛的应用。本文主要讨论了使用目前比较流行的CORBA中间件技术和WebLogic应用平台以及EJB处理业务的能力,设计实现一个支持Web分布式应用的电子商务系统的方法。     

基于构件的电子商务

电子商务系统的设计多采用三层体系结构。文中针对三层体系结构存在的缺点，介绍了一种基构件的四层体系结构的设计方法，分析了这种方法方法的特点，并给出了一个实例说明。     

基于J2EE架构的电子商务平台的设计与实现

随着电子商务时代的来临和Web技术的迅速发展,传统开发平台已无发满足电子商务系统的要求。J2EE作为一种成熟的分布式体系结构,为电子商务系统的开发提供了一种高效的企业级应用解决方案。本文阐述了J2EE多层体系架构、技术框架,并分析基于J2EE架构下、采用多层体系结构、分布式组件技术的电子商务应用的优点。最后,以网上电子书店为例,简述了如何利用J2EE开发高效的、可扩展的电子商务平台。     

一体化机群操作系统Phoenix

从操作系统的角度完备地定义了一体化机群功能软件Phoenix的体系结构,将机群操作系统分为异构资源、机群操作系统核心、用户环境3个层次,综合用户环境的核心需求,定义了机群操作系统核心的结构,并且基于组服务保证了机群操作系统核心的容错和可扩展特性．在机群操作系统核心的基础上构造了满足于不同用户需求的用户环境．Phoenix在曙光4000A高性能计算机系统上得到了应用．     

电子商务系统的容量规划

本文提出了一种确定电子商务系统容量的方案:该方案基于主流技术J2ee,WebLogic的实际软件环境中,从服务器硬件、LAN基础结构、外部网络连通性三个方面确定一个电子商务系统实际案例的系统容量,实验数据和该实际案例日后的运行情况表明,在该容量规划方案的指导下搭建的系统运行环境可以保证电子商务系统的正常运行。     

浅谈PALcode在Alpha体系结构中的作用

在Ａｌｐｈａ体系结构设计中，为了精简指令，提高整体性能，使Ａｌｐｈａ系统适用于我种系统软件，将氏层的硬件设计对高层软件透明，创造地采用了ＰＡＬｃｏｄｅ设计方案，本文简要介绍了ＰＡＬｃｏｄｅ在Ａｌｐｈａ体系结构中的作用，它和软件、硬件之间的关系，以及它在内存中的位置与调用方式。     

基于机群技术的邮件过滤系统设计

文中提出了基于机群技术的网络垃圾邮件过滤系统SFS,给出了邮件过滤系统体系结构及软件层次结构.该系统的体系结构具有可扩展性,能够适应于各种带宽网络的垃圾邮件过滤,同时支持对于垃圾邮件的自动发现和实时拦截两种功能.     

电子商务的技术及其应用

该文探讨了基于Web数据库的四层结构B/S模式的电子商务系统的体系结构,企业间电子商务服务器的拓扑图,以及基于ASP/ADO的Web数据库的访问技术。     

SCA硬件抽象层接口设计

随着软件通信体系结构的广泛研究和应用,为在包含特定硬件单元的SCA硬件平台上实现不同计算单元上组件间管理的统一性和通信的标准化,提高波形应用在不同的硬件平台上的可移植性和重用性,软件通信体系结构引入了硬件抽象层的概念.该文以通用处理器和DSP为例,描述硬件抽象层的功能及其在通用处理器GPP和DSP上的API实现.     

计算机体系结构软件模拟技术的现状与未来

计算机体系结构软件模拟技术主要是为了迎合高性能计算机的研发而采取的在现有平台上对体系设计情况进行验证和模拟的过程.它可以充分发挥模拟软件成本低,可以有效发现计算机硬件系统存在的问题等优势,从而为计算机设计提供最优秀的方案.本文从计算机体系结构软件模拟技术的应用现状出发,重点探讨计算机体系结构软件模拟技术的未来应用前景.     

EOS: a real-time operating system adapts to applicationarchitectures

Rather than dictating the architecture of application software and hardware, a real-time operating system should be flexible enough to adapt to the application's needs. The EOS real-time operating system provides a modular, scalable software platform users can tailor to specific custom hardware architectures. Developers can use minimum configurations of EOS for simple systems or enhance it with their own code for complex systems. Ultimately, we provide a configurable software platform that helps embedded application developers create low-cost, time-effective products     

Computer-aided hardware-software codesign

Most digital systems consist of a hardware component and software programs that execute on the hardware platform. Obviously, a system can deliver higher performance when we tune the hardware to its software applications and vice versa. Today's novel architectures and the possible use of computer-aided design tools have created new opportunities to find solutions to codesign problems. This survey addresses this challenge, considers different architectures and their uses, and reports on the status of CAD codesign tools, with particular reference to simulation and synthesis     

Seeking solutions in configurable computing

Configurable computing offers the potential of producing powerful new computing systems. Will current research overcome the dearth of commercial applicability to make such systems a reality? Unfortunately, no system to date has yet proven attractive or competitive enough to establish a commercial presence. We believe that ample opportunity exists for work in a broad range of areas. In particular, the configurable computing community should focus on refining the emerging architectures, producing more effective software/hardware APIs, better tools for application development that incorporate the models of hardware reconfiguration, and effective benchmarking strategies     

Portability in MAC protocol and transceiver software implementations for LR‐WPAN platforms

In a variety of emerging networked computing system domains over the years, there have been bursts of activity on new medium access control (MAC) protocols, as new communication transceiver technologies with greater data‐movement performance or lower power dissipation have been introduced. To enable implementations flexible to evolving standards and improving application‐domain insight, such MAC protocols are typically initially implemented in software, and interface between applications or system software, typically executing on an embedded processor or microcontroller, and the evolving radio transceiver hardware. Many challenges exist in implementing MAC protocols across evolving or competing transceiver hardware implementations and processor architectures. Some of these challenges are peculiar to the requirements of MAC protocols, and others are a result of the plethora of system and processor architectures in the embedded systems domain. This article studies the challenges facing software implementations of MAC protocols running on embedded microcontrollers, and interfacing with radio transceiver hardware. Experience with an implementation of the IEEE 802.15.4 MAC across three hardware platforms with different processor, system, and systems software architectures is presented, focusing on implementation approach and interfaces. Pitfalls are pointed out, and guidelines are provided for ensuring that new MAC implementations are easily portable across processor architectures and transceiver hardware. Copyright © 2010 John Wiley & Sons, Ltd.     

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally we will summarize the concept combined with an outlook on further investigations.     

Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems

Rapid changes in platform hardware resources with the evolution of many-core architectures will require a fundamental reexamination of mainstream system-software design decisions to support multiple cores and to efficiently manage on-chip hardware resources shared among the multiple cores. In turn, the evolution of many-core processor architectures will be successfully sustained by the new capabilities and features added to the system software, perhaps while requiring substantial support from hardware. The guest editors introduce five articles on the interaction of computer architecture and operating systems for this special issue of IEEE Micro.     

A comparative evaluation of hybrid distributed shared-memory systems

Distributed Shared-Memory (DSM) systems are shared-memory multiprocessor architectures in which each processor node contains a partition of the shared memory. In hybrid DSM systems coherence among caches is maintained by a software-implemented coherence protocol relying on some hardware support. Hardware support is provided to satisfy every node hit (the common case) and software is invoked only for accesses to remote nodes.In this paper we compare the design and performance of four hybrid distributed shared memory (DSM) organizations by detailed simulation of the same hardware platform. We have implemented the software protocol handlers for the four architectures. The handlers are written in C and assembly code. Coherence transactions are executed in trap and interrupt handlers. Together with the application, the handlers are executed in full detail in execution-driven simulations of six complete benchmarks with coarse-grain and fine-grain sharing. We relate our experience implementing and simulating the software protocols for the four architectures.Because the overhead of remote accesses is very high in hybrid systems, the system of choice is different than for purely hardware systems.     

嵌入式系统的软硬件划分

嵌入式系统软硬件协同设计中的关键步骤之一是软硬件划分。现有的许多软硬件划分方法都试图捕获太多有关划分问题和目标结构的细节，可扩展性差。本文提出了一种简化的软硬件划分问题模型，这种简化模型能分别对不同的划分问题进行形式化定义。在此模型的基础上，本文给出了基于ILP的算法和遗传算法。实验结果表明，我们的遗传算法能有效地解决千万个节点规模的划分问题，并获得近似最优解。     

An event-based architecture definition language

This paper discusses general requirements for architecture definition languages, and describes the syntax and semantics of the subset of the Rapide language that is designed to satisfy these requirements. Rapide is a concurrent event-based simulation language for defining and simulating the behavior of system architectures. Rapide is intended for modelling the architectures of concurrent and distributed systems, both hardware and software in order to represent the behavior of distributed systems in as much detail as possible. Rapide is designed to make the greatest possible use of event-based modelling by producing causal event simulations. When a Rapide model is executed it produces a simulation that shows not only the events that make up the model's behavior, and their timestamps, but also which events caused other events, and which events happened independently. The architecture definition features of Rapide are described: event patterns, interfaces, architectures and event pattern mappings. The use of these features to build causal event models of both static and dynamic architectures is illustrated by a series of simple examples from both software and hardware. Also we give a detailed example of the use of event pattern mappings to define the relationship between two architectures at different levels of abstraction. Finally, we discuss briefly how Rapide is related to other event-based languages     

Learning in analog neural network hardware

Hardware implementations of neuroprocessor architectures are currently enjoying commercial availability for the first time ever. This development has been caused in part by the requirement for real-time solutions to time critical neural network applications. Massively parallel asynchronous neuromorphic representations are inherently capable of very high computational speeds when properly cast in the “right stuff”, i.e. electronic or optoelectronic hardware. However, hardware based learning in such systems is still at a primitive stage. In practise, simulations are typically performed in software, and the resulting synaptic weight capturing the input-output transformation subsequently quantized and down-loaded onto the neural hardware. However, because of the numerous discrepancies between the software and hardware, such systems are inherently poor in performance. In this paper we report on chip-in-the-loop learning systems assembled from custom analog “building blocks” hardware.