Optimizing image spatial filtering on single CPU core

Nowadays, computing becomes a service on cloud computing resources. Users reserve virtual machines to execute their applications with minimum number of processing cores to save money. Optimizing user applications on the level of single core of a physical machine is highly desirable to users to reduce cost, as well as to cloud providers to reduce power consumption. In this paper, we showed how to exploit all the processing resources available in a single CPU physical core to optimize the performance of the 2D spatial filtering operation, a basic kernel in important image and multimedia applications such as image enhancement, edge detection, image segmentation, and image analysis. We proposed a novel computational procedure to restructure the conventional image filtering operation. Then, we demonstrated the merits of combining hand-optimized source-code restructuring, auto-optimized compiler techniques including vectorization, and hand-optimized threading to squeeze the performance of a single CPU core. Our intensive performance evaluations, using Sobel filters, on a variety of image sizes using the Linux Perf tool on a single core of the quad-core Intel Core i7 processor showed that our source-code restructurings with compiler auto-vectorization, using Intel AVX vector instructions, is 1.3X better than the non-restructured auto-vectorized version of the CImg library for computing the image gradient. Moreover, using OpenMP library directives we studied different image partitioning strategies to better exploit the two hardware threads inside a CPU core which boosted performance to 2.6X. Compared with the conventional CImg implementation, we obtained an average enhancement of 5.0X for image sizes ranging from 0.5 MPixel to 8 MPixel. However, comparing our best-optimized code to the conventional non-optimized serial code, without threading, resulted in a significant enhancement of 23X. The overall results showed how significant performance in important image processing applications can be obtained by applying source-code restructurings before employing any automatic compiler optimizations to exploit ILP, DLP and TLP parallelism degrees inside a single core of a multi-core CPU.     

CPU

对于用户而言,现在是个新老CPU交接换代的前夜。英特尔SandyBridge架构和AMD的Bulldozer（推土机）架构已经处于箭在弦上、引而待发的状态。从目前的市场现状来看,英特尔在架构和工艺上都占有优势,但AMD也适时地推出了原生六核和低价策略来对抗,在一场大的架构升级即将来临之际,     

The HP PA-8000 RISC CPU

The PA-8000 RISC CPU is the first of a new generation of Hewlett-Packard microprocessors. Designed for high-end systems, it is among the world's most powerful and fastest microprocessors. It features an aggressive, four-way, superscalar implementation, combining speculative execution with on-the-fly instruction reordering. The heart of the machine, the instruction reorder buffer, provides out-of-order execution capability. Our primary design objective for the PA-8000 was to attain industry-leading performance in a broad range of applications. In addition, we wanted to provide full support for 64-bit applications. To make the PA-8000 truly useful, we needed to ensure that the processor would not only achieve high benchmark performance but would sustain such performance in large, real-world applications. To achieve this goal, we designed large, external primary caches with the ability to hide memory latency in hardware. We also implemented dynamic instruction reordering in hardware to maximize instruction-level parallelism available to the execution units. The PA-8000 connects to a high-bandwidth Runway system bus, a 768-Mbyte/s split-transaction bus that allows each processor to generate multiple outstanding memory requests. The processor also provides glueless support for up to four-way multiprocessing via the Runway bus. The PA-8000 implements the new PA (Precision Architecture) 2.0, a binary-compatible extension of the previous PA-RISC architecture. All previous code executes on the PA-8000 without recompilation or translation     

CPU监视器电路的研制

CPU监视器电路包含了电压监控、上电复位、看门狗定时和串行E2PROM四种功能,电路具有多功能、反应速度快、抗干扰能力强等特点。下文主要介绍了该电路的工作原理和相关的设计、工艺等技术。     

嵌入式CPU的存储器管理单元

随着嵌入式技术的不断发展,对嵌入式CPU的要求越来越高,而存储器管理单元是嵌入式CPU不可或缺的重要组成部分,它允许程序员使用虚拟地址进行编程,简化了任务编程。深入了解存储器管理单元MMU的工作原理和基本结构对嵌入式开发大有好处。     

CPU桥ASIC设计中CPU模拟器的设计

功能模拟是设计高性能微处理器接口ＡＳＩＣ芯片的重要环节,目的是消除ＡＳＩＣ的功能性设计错误。为了更好地对ＡＳＩＣ芯片进行模拟,需要灵活、方便、能够体现微处理器行为的ＣＰＵ模型,文章将介绍了对一个ＣＰＵ行为模拟器的开发。     

CPU 探秘

现代社会瞬息万变,是一个信息时代,家庭拥有一台个人电脑(PC Person computer)已是非常平常,众所周知,中央处理器(CPU Central Processing Unit)电脑的心脏,是整个计算机系统的核心,它往往决定着电脑的档次,如昔日的286、386、486,到今天的Pentium、Pentium Ⅱ、Pentium Ⅲ、Pentium Ⅳ、K6、K7等.回顾CPU发展的历史长河,从雏形到今天,制造技术已经极大提高,主要表现集成电子光件越来越多,开时时集成几千个晶体管,现在有几百万、几千万个晶体管,这么多晶体管,它们是如可实现电脑功能、处理电脑数据的?本文对CPU如何工作进行了一些探索.     

嵌入式CPU指令Cache的设计与实现

针对嵌入式CPU指令处理速度与存储器指令存取速度不匹配问题,本文基于FPGA设计并实现了可以有效解决这一问题的指令Cache.根据嵌入式五级流水线CPU特性,所设计指令Cache的地址映射方式采用需要资源较少的直接映射(Direct Mapping),替换算法采用速度较快的先进先出(FIFO);使用VHDL实现指令Cache;对所设计指令Cache进行功能仿真和时序仿真并给出功能仿真结果.仿真结果表明了所设计指令Cache的有效性.     

CPU bugs, CPU backdoors and consequences on security

In this paper, we present the security implications of x86 processor bugs or backdoors on operating systems and virtual machine monitors. We will not try to determine whether the backdoor threat is realistic or not, but we will assume that a bug or a backdoor exists and analyze the consequences on systems. We will show how it is possible for an attacker to implement a simple and generic CPU backdoor in order—at some later point in time—to bypass mandatory security mechanisms with very limited initial privileges. We will explain practical difficulties and show proof of concept schemes using a modified Qemu CPU emulator. Backdoors studied in this paper are all usable from the software level without any physical access to the hardware.     

The Real Cost of a CPU Hour

IT organizations can now outsource computer hardware by leasing CPU time through cloud computing services. A proposed modeling tool can quantitatively compare the cost of leasing CPU time from these online services to that of purchasing and using a server cluster of equivalent capability.     

CPU养护有道

电脑的发展正发生着日复一日的变化,随着电脑功能的不断加深,承担电脑程序运算的中央处理器即DIYer们常挂在口边的CPU就显得十分的重要。因此,在DIYer们为是选购Intel的P4还是AMD的XP烦恼时,大家是否也应该考虑一下对CPU来说至关重要的其他因素。我们只有把握住这些因素,才能够对CPU养护有道。散热为先高性能产生高热量,不断提升频率的CPU在给电脑带来了更高速度的同时,也伴随着产生了高热量。对1500MHz以上的CPU来说,做好散热工作是必不不可少的。如何做呢,我们主要依靠散热风扇。因此,在电脑选购的时候,切莫忘记对散热风扇的…     

SONY HDR-XR520E

HDR—XR520E是当前索尼最高端的家用硬盘摄像机。作为旗舰级产品,HDR—XR520E配置自然很高,它使用了一块索尼最新研制的1／2．88英寸,“ExmorR”CMOS图像传感器。     

SPEC CPU2000: measuring CPU performance in the New Millennium

As computers and software have become more powerful, it seems almost human nature to want the biggest and fastest toy you can afford. But how do you know if your toy is tops? Even if your application never does any I/O, it's not just the speed of the CPU that dictates performance. Cache, main memory, and compilers also play a role. Software applications also have differing performance requirements. So whom do you trust to provide this information? The Standard Performance Evaluation Corporation (SPEC) is a nonprofit consortium whose members include hardware vendors, software vendors, universities, customers, and consultants. SPEC's mission is to develop technically credible and objective component- and system-level benchmarks for multiple operating systems and environments, including high-performance numeric computing, Web servers, and graphical subsystems. On 30 June 2000, SPEC retired the CPU95 benchmark suite. Its replacement is CPU2000, a new CPU benchmark suite with 19 applications that have never before been in a SPEC CPU suite. The article discusses how SPEC developed this benchmark suite and what the benchmarks do     

一种带Cache的嵌入式CPU的设计与实现

基于FPGA平台实现了嵌入式RISC CPU的设计.根据项目要求,实现指令集为MIPS CPU指令集的一个子集,分析指令处理过程,构建了嵌入式CPU的5级数据通路.分析了流水线产生的相关性问题,采用数据前推技术和软件编译结合的解决方案.给出了控制单元、运算单元、指令Cache的实现与设计.在FPGA平台上实现并验证了CPU的设计.     

CPU使用时间100%全面分析

CPU使用时间100%是计算机使用中经常遇到的问题,本文通过软件、硬件两个角度全面分析常见的10种CPU使用时间100%的问题和解决方法。