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1.
提出了一种基于DNA自动机的串行二进制进位加法的实现方法。对于一位二进制的进位加法,通过预先设计的DNA自动机模型在一个试管中以自动机的方式完成。对于”位二进制的进位加法,通过将n个类似的试管按照从低位到高位的顺序组成串行网络;将低位加法操作产生的进位转移到高位试管,组成高位自动机的输入符号串,完成高位的加法操作。这种运算方式类似于电子计算机中加法运算系统,为DNA计算机实现算术运算提供了一种新颖的方法。  相似文献   

2.
为加快密码系统中大数加法的运算速度,提出并实现一种基于组间进位预测的快速进位加法器。将参与加法运算的大数进行分 组,每个分组采用改进的超前进位技术以减少组内进位延时,组间通过进位预测完成不同进位状态下的加法运算,通过每个组产生的进位状态判断最终结果。性能分析表明,该进位加法器实现1 024位大数加法运算的速度较快。  相似文献   

3.
本文描述了二进制并行加法器的高速进位电路。电路由串联连接的射极跟随器组成,形成加法器各位进位信号的传输通路。 利用通用电路分析程序,对8级单块集成进位电路进行计算机模拟,预计每级进位延迟0.25毫微秒。 具有射极跟随器进位电路的8级加法器实验装置产生的每级进位延迟小于0.6毫微秒。用计算机模拟实验进位电路得到的结果与实际测量极其一致。实验电路性能和模拟单块电路性能之间的差别,是由于寄生负载不同。 对于采用单块进位电路的两个24位数和24个TTL全加器级,整个加法时间是22毫微秒,其中17毫微秒为传送通过第一级加法器需要的时间。  相似文献   

4.
本文将电子计算机中加法功能的进位部份特别抽出用逻辑代数加以描述,文中叙述了用晶体管、二极管、脈冲变压器构成这种功能的进位电路于一拍时鐘脈冲的间隔内完成,并采用元件数量比较少的并行加法器,使加法速度飞跃地上升。其次,还谈到用于二进位的情况,也叙述了用到十进位的效果。考虑到科学计算上所需耍的位数制成了一个40位的进位电路,所得的工作特性很好。  相似文献   

5.
加法速度是数字计算机性能的主要指标之一,从最低位到最高位进位信号的传送速度使并行电路运算速度受到限制,这是最坏情况。以前为了缩短它的进位时间提高运算速度,已经采取了很多办法。这些方法大致可分二种,一种是增加运算电路邏辑结构,一种是使进位电路本身高速化。 前一种方法最简单,这种方法有: 第一个方法是在基本电路的多道输入和多道输出端的范围内使各位的进位尽可能同时进  相似文献   

6.
在一个适用于“加”,“与”,“或”及“异或”操作的算术及逻辑单元中,加法根据和信息依赖于进位的原则进行,而在执行逻辑操作时,函数发生器产生与各种操作有关的操作数位奇偶函数。加法的各进位或逻辑操作的各奇偶函数在校验电路中进行组合以产生不依赖于所形成和的结果预测奇偶。校验电路的工作与作那种操作有关,结果位奇偶与预测奇偶相比较以校验结果是否有错。  相似文献   

7.
这里介绍一个能同时完成加法和进位传送的高速加法器线路。一般的加法技术中,通常都是把进位与加法操作分开来处理。甚至在所谓“同时进位”的线路中,进位传送时间也达到了两倍到十倍的正常加法时间。此处介绍的新方法是把加法过程分为“加进位”或“加无进位”的操作。加法指令脉冲可在这两条线中的一条上传送,但不能同时都有。当加法过程结束了,进位传送也就结束。在连续的加法操作之间不要求有  相似文献   

8.
李云锋  赵金薇  周汇  俞军 《计算机工程》2007,33(24):242-243
冗余符号数加法器满足了对加法器高速度和高精度的要求。该文针对二进制符号数加法传统算法的不足,提出了一种改进算法,设计了相应的加法电路。它采用3级结构实现加法器,结构简单而规则,中间进位与中间和都仅需要1bit编码。与传统结构相比,该算法实现的电路速度更快、面积更小、动态功耗更少。  相似文献   

9.
基于三值光计算机的并行无进位加法   总被引:2,自引:0,他引:2  
在三值光计算机(其核心是一块体积为38.0×65.5×2.2 mm~3、能耗为0.3mw的单色液晶显示器及其两侧的偏振片)上以全并行方式实现了两向量无进位光学加法。为利用光的并行性,在MSD(Modified Signed-Digit)数字系统上通过定义4个变换,分3步实现了全并行无进位加法。加法所需时间与操作数的位数无关。通过实验证明了三值光计算机并行无进位加法运算的可行性和正确性。该系统能以全并行的方式完成两个680位的MSD数加法运算。  相似文献   

10.
在计算中加法操作的检验是很重要的。因此,已经有了一些检验方法。其中一种是独立校验,另一种是利用加法操作时产生的信息进行检验。后者已经用于一些计算机的设计中。这里要介绍的是一种检验在相加过程中产生的进位的奇偶预测法。它与已有方法的区别在于:当进行检验时,不需要双重进位线路。  相似文献   

11.
The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.  相似文献   

12.
唐敏  许团辉  王玉艳 《计算机工程》2011,37(10):219-220
传统的加法器在有符号数相加时需将操作数转化为补码形式进行运算,运算结束将计算结果再转化为原码。为减少关键路径延迟,在标志前缀加法器的基础上,提出一种改进的反码加法器,将常用反码加法器中的加一单元合并到加法运算中。在SMIC 0.18 μm工艺下,将改进的64位反码加法器与常用的64位补码加法器进行比较,数据显示面积减少了39.1%,功耗降低了39.9%,关键路径延迟降低了5.1%。结果表明,改进的反码加法器性能较优。  相似文献   

13.
Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is (log n). To achieve a minimum critical path delay lower than (log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.  相似文献   

14.
The time optimization of the combinational adder of the decimal digits encoded in the Johnson-Mobius code is performed. A number of structural variants of the decimal adder are proposed and analyzed. The implementation of the optimal variant of the adder using quantum-dot cellular automata is described. A successful computer simulation of the adder is performed. The estimations of the hardware costs and the signal propagation delay are given in comparison with the original version of the adder developed earlier by the author.  相似文献   

15.
Lane of parallel through carry in ternary optical adder   总被引:7,自引:0,他引:7  
At the present 50 to 100 microseconds are necessary for a liquid crystal to change its state from opacity to clarity; 1.14×10-5 microseconds are however proved to be enough for light to pass through a clarity liquid crystal device. Rooted from this great difference in time, an optical adder was constructed with parallel through carry lanes (PTCL) composed of liquid crystals. Because all carries in PTCL process in parallel, the carry delay in the ternary optical computer's adder is avoided. Eliminating the carry delay in adder of ternary optical computer by physical means, the PTCL is also applicable for other types of optical adders. Moreover a light diagram of the adder and one PTCL structure are provided.  相似文献   

16.
描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构,可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点,使得加法器的面积和连线减少了50%,而延时与加法器的长度的对数成正比。仿真结果表明,在典型工作条件下,采用0.18μm工艺库标准单元,其关键路径的延时为0.83ns,面积为0.149mm2,功耗仅为0.315mW。  相似文献   

17.
Ahmet   《Journal of Systems Architecture》2008,54(12):1129-1142
Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.  相似文献   

18.
Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.  相似文献   

19.
设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18μm工艺库标准单元,其延时降低46%,功耗降低5%。  相似文献   

20.
IoT provides a platform for every device to be connected by means of a stable internet connection. The interoperability of the devices helps to communicate and exchange data between one another and increases the power consumption of devices. When creating a new IoT system or rebuilding the existing ones, the low power circuit design is considered as an essential factor. In the low power circuit design, the most challenging aspect to overcome is to reduce the leakage power, because the battery-operated devices are fast in draining energy when left long in the standby mode. Reducing the delay of a ripple carry adder can be only accomplished with Carry-Skip Adder (CSA) with minimal effort when compared to other techniques like a carry-look ahead adder. The carry skip adder belongs to the family of bypass adders, and its main aim is to improve the worst-case delay of the IoT device based on its area and power consumption. The CSA used in the proposed method for the IoT processor helps to increase the performance of the system relative to average power dissipation, leakage power, power delay product, and propagation delay.  相似文献   

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