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1.
The capability to perform fast load-following has been an important issue in the power industry. An output tracking control system of a boiler-turbine unit is developed. The system is composed of stable inversion and feedback controller. The stable inversion is implemented as a feedforward controller to improve the load-following capability, and the feedback controller is utilized to guarantee the stability and robustness of the whole system. Loop-shaping H∞ method is used to design the feedback controller and the final controller is reduced to a multivariable PI form. The output tracking control system takes account of the multivariable, nonlinear and coupling behavior of boiler-turbine system, and the simulation tests show that the control system works well and can be widely applied.  相似文献   

2.
The capability to perform fast load_following has been an important issue in the power industry. An output tracking control system of a boiler_turbine unit is developed. The system is composed of stable inversion and feedback controller. The stable inversion is implemented as a feedforward controller to improve the load_following capability, and the feedback controller is utilized to guarantee the stability and robustness of the whole system. Loop_shaping H_∞ method is used to design the feedback controller and the final controller is reduced to a multivariable PI form. The output tracking control system takes account of the multivariable, nonlinear and coupling behavior of boiler_turbine system, and the simulation tests show that the control system works well and can be widely applied.  相似文献   

3.
CAN-based synchronized motion control for induction motors   总被引:1,自引:0,他引:1  
A control area network (CAN) based multi-motor synchronized motion control system with an advanced synchronized control strategy is proposed. The strategy is to incorporate the adjacent cross-coupling control strategy into the sliding mode control architecture. As illustrated by the four-induction-motor-based experimental results, the multi-motor synchronized motion control system, via the CAN bus, has been successfully implemented. With the employment of the advanced synchronized motion control strategy, the synchronization performance can be significantly improved.  相似文献   

4.
Linearizing control of induction motor based on networked control systems   总被引:1,自引:1,他引:0  
A new approach to speed control of induction motors is developed by introducing networked control systems (NCSs) into the induction motor driving system. The control strategy is to stabilize and track the rotor speed of the induction motor when the network time delay occurs in the transport medium of network data. First, a feedback linearization method is used to achieve input-output linearization and decoupling control of the induction motor driving system based on rotor flux model, and then the characteristic of network data is analyzed in terms of the inherent network time delay. A networked control model of an induction motor is established. The sufficient condition of asymptotic stability for the networked induction motor driving system is given, and the state feedback controller is obtained by solving the linear matrix inequalities (LMIs). Simulation results verify the efficiency of the proposed scheme.  相似文献   

5.
A ship, as an object of course control, is characterized by a nonlinear function describing the static maneuvering characteristics. The backstepping method is one of the methods that can be used during the designing process of a nonlinear course controller for ships. The method has been used for the purpose of designing two configurations of nonlinear controllers, which were then used to control the ship course. One of the configurations took dynamic characteristic of a steering gear into account during the designing stage. The parameters of the obtained nonlinear control structures have been tuned to optimise the operation of the control system. The optimisation process has been performed by means of genetic algorithms. The quality of operation of the designed control algorithms has been checked in simulation tests performed on the mathematical model of a tanker. The results of simulation experiments have been compared with the performance of the system containing a conventional proportional-derivative (PD) controller.  相似文献   

6.
In this paper, an efficient scheme for recognition of handwritten Odia numerals using hidden markov model (HMM) has been proposed. Three different feature vectors for each of the numeral is generated through a polygonal approximation of object contour. Subsequently, aggregated feature vector for each numeral is derived from these three primary feature vectors using a fuzzy inference system. The final feature vector is divided into three levels and interpreted as three different states for HMM. Ten different three-state ergodic hidden markov models (HMMs) are thus constructed corresponding to ten numeral classes and parameters are calculated from these models. For the recognition of a probe numeral, its log-likelihood against these models are computed to decide its class label. The proposed scheme is implemented on a dataset of 2500 handwritten samples and a recognition accuracy of 96.3% has been achieved. The scheme is compared with other competent schemes.  相似文献   

7.
Brain-computer interfaces (BCIs) can provide direct bidirectional communication between the brain and a machine. Recently, the BCI technique has been used in seizure control. UsuMly, a closed-loop system based on BCI is set up which delivers a therapic electrical stimulus only in response to seizure onsets. In this way, the side effects of neurostimulation can be greatly reduced. In this paper, a new BCI-based responsive stimulation system is proposed. With an efficient morphology-based seizure detector, seizure events can be identified in the early stages which trigger electrical stimulations to be sent to the cortex of the brain. The proposed system was tested on rats with penicillin-induced epileptic seizures. Online experiments show that 83% of the seizures could be detected successfully with a short average time delay of 3.11 s. With the therapy of the BCI-based seizure control system, most seizures were suppressed within 10 s. Compared with the control group, the average seizure duration was reduced by 30.7%. Therefore, the proposed system can control epileptic seizures effectively and has potential in clinical applications.  相似文献   

8.
A new on-line fault detection and isolation (FDI) scheme proposed for engines using an adaptive neural network classifier is evaluated for a wide range of operational modes to check the robustness of the scheme in this paper. The neural classifier is adaptive to cope with the significant parameter uncertainty, disturbances, and environment changes. The developed scheme is capable of diagnosing faults in on-line mode and the FDI for the closed-loop system with can be directly implemented in an on-board crankshaft speed feedback is investigated by diagnosis system (hardware). The robustness of testing it for a wide range of operational modes including robustness against fixed and sinusoidal throttle angle inputs, change in load, change in an engine parameter, and all these changes occurring at the same time. The evaluations are performed using a mean value engine model (MVEM), which is a widely used benchmark model for engine control system and FDI system design. The simulation results confirm the robustness of the proposed method for various uncertainties and disturbances.  相似文献   

9.
This paper describes a new scheme for feature extraction from facial images on FPGA. The proposed method is comprised of two stages. The first stage uses the 5/3 DWT to decompose the original face image into LL, LH, HL, and HH wavelet coefficient to reduce the size of the image. In the second stage, PCA is employed to extract the face features from the wavelet coefficients. Here we use the power iteration algorithm to find the eigenvector of the covariance matrix. We present an efficient hardware architecture using combination of parallel processing module and serial processing module. This method can take the benefits of parallel usage advantage of FPGAs and can save hardware resources. Complete hardware implemented on a Stratix II FPGA. The experimental results show that the system works with high processing rate and only 21% of the logic resources an FPGA are consumed by face recognition logic Thus it is very suitable for the low cost implementation of the face recognition system.  相似文献   

10.
Discrete linear quadratic control has been efciently applied to linear systems as an optimal control.However,a robotic system is highly nonlinear,heavily coupled and uncertain.To overcome the problem,the robotic system can be modeled as a linear discrete-time time-varying system in performing repetitive tasks.This modeling motivates us to develop an optimal repetitive control.The contribution of this paper is twofold.For the frst time,it presents discrete linear quadratic repetitive control for electrically driven robots using the mentioned model.The proposed control approach is based on the voltage control strategy.Second,uncertainty is efectively compensated by employing a robust time-delay controller.The uncertainty can include parametric uncertainty,unmodeled dynamics and external disturbances.To highlight its ability in overcoming the uncertainty,the dynamic equation of an articulated robot is introduced and used for the simulation,modeling and control purposes.Stability analysis verifes the proposed control approach and simulation results show its efectiveness.  相似文献   

11.
Diode clamped multi-level inverter (DCMLI) has a wide application prospect in high-voltage and adjustable speed drive systems due to its low stress on switching devices, low harmonic output, and simple structure. However, the problem of complexity of selecting vectors and capacitor voltage unbalance needs to be solved when the algorithm of direct torque control (DTC) is implemented on DCMLI. In this paper, a fuzzy DTC system of an induction machine fed by a three-level neutral-point-clamped (NPC) inverter is proposed. After introducing fuzzy logic, optimal selecting switching state is realized by applying various strategies which can distinguish the grade of the errors of stator flux linkage, torque, the neutral-point potential, and the position of stator flux linkage. Consequently, the neutral-point potential unbalance, the dv/dt of output voltage and the switching loss are restrained effectively, and desirable dynamic and steady-state performances of induction machines can be obtained for the DTC scheme. A design method of the fuzzy controller is introduced in detail, and the relevant simulation and experimental results have verified the feasibility of the proposed control algorithm.  相似文献   

12.
徐卓  王雪静  叶凡  任俊彦 《计算机工程》2008,34(18):117-119
提出一种应用于多波段正交频分复用(MB-OFDM)超宽带通信系统的维特比解码器的设计方案,分析MB-OFDM所采用的卷积/凿孔码及相应的维特比解码算法的性能。为了达到系统要求的最高数据传输率、保持硬件开销的经济性,结合滑动窗口和折叠2种方法设计解码器的硬件结构。在低速工作模式下,部分处理单元被禁用,以节省功耗。该设计经Xilinx Virtex-4 FPGA验证,最高译码速率可达432 Mb/s。  相似文献   

13.
分块自适应量化算法的FPGA实现   总被引:2,自引:1,他引:2  
详细介绍了采用FPGA实现分块自适应量化(BAQ)算法的设计方法。该设计选用Xilinx公司100万门FPGA,采用自顶向下的方法,实现了3位长BAQ压缩算法。设计中通过资源共享来降低资源消耗,通过并行和流水来提高处理速度,满足了星载系统小型化、低功耗和高可靠性的要求。与专用DSP方案相比,采用FPGA的实现方案极大地简化了电路设计的复杂性和布线的难度。  相似文献   

14.
崔强强  金同标  朱勇 《计算机应用》2011,31(9):2385-2388
研究了大素数域上的椭圆曲线加密算法,基于IMPULSE C语言,对该算法进行编程实现;在标准射影坐标系下,对点加和倍加算法进行并行化改进,并且在编程时利用编译器特性做了进一步的并行化。通过对加密算法合理的软硬件分割,将计算量大而且复杂的点乘运算作为硬件部分,通过现场可编程门陈列(FPGA)进行硬件加速;将加密协议的其他部分作为软件部分,在传统CPU上执行,并将硬件部分生成VHDL代码。分别进行加密算法的CoDeveloper的桌面仿真和生成的硬件VHDL代码的ISE综合仿真。最后将该加速设计在Xilinx Virtex-5 xc5vfx70t FPGA开发板上作了实现,基于FPGA的实验结果表明,P-192上点乘运算处理在133MHz时钟下用时2.9 ms,硬件资源分配合理,与现有的手工编写的HDL代码相比,具有并行加速优势。  相似文献   

15.
正规基中模乘算法的FPGA实现方法研究   总被引:1,自引:0,他引:1  
给出了GF(2m)上椭圆曲线密码系统中最佳正规基表示的模乘运算优化算法,提出了该算法的FPGA实现方案,并详细分析了实现该算法的有限状态机模型。结合Xilinx的FPGA器件,用VerilogHDL编写了实现该有限状态机的代码,在ISE和ModelSim开发工具中通过仿真、综合。试验表明,该文实现的模乘方案较其他实现方案具有较高的速度,并在EC-Elgamal密码体系中得到较好的应用。  相似文献   

16.
This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240." The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented  相似文献   

17.
18.

In this paper, we proposed a novel low power and high-speed FPGA implementation of the 4D memristor chaotic system with cubic nonlinearity based on Xilinx System Generator (XSG) model. Firstly, a pseudo-random number generator based on the proposed XSG FPGA implementation of the proposed 4D memristor chaotic system which implemented into Xilinx Spartan-6 X6SLX45 board with 32 fixed-point format. The aim of the FPGA implementation is increasing the frequency of the memristor chaotic random number generators. The FPGA implementation of the memristor chaotic system results show that the new design approach achieves a maximum frequency of 393 MHz and dissipates 117 m watt. The standard fifteen randomization tests are used to measure the quality of the proposed pseudo-random number generator based on the 4D memristor chaotic system and it gives an excellent randomization analysis. Also, the gray image encryption scheme based on the 4D memristor chaotic system has been introduced. The proposed cryptosystem has a large keyspace, very low correlation values, high entropy which is much closer to the ideal entropy value, a high number of pixels change rate and high unified average changing intensity values. The results and security analysis of the proposed encryption scheme demonstrate that the investigated encryption approach can protect high speed and high security against various attack.

  相似文献   

19.
This paper presents a new approach to manage data content of memories implemented in FPGAs through the configuration bitstream. The proposed approach is able to read and write the data content from Block RAMs (BRAMs) in FPGA based designs by reading and processing the information stored in the bitstream. Thanks to this method it is possible to extract, load, copy or compare the information of BRAMs without neither resource overhead nor performance penalty in the design. It can also be applied to existing designs without the need of re-synthesizing. Due to its advantages it becomes an interesting tool to carry out several applications, such as error detection and recovery or fault injection. It also opens the doors to the design of cutting-edge applications. The approach has been implemented in a Xilinx ZYNQ System-on-Chip (SoC) device, which combines an FPGA and an ARM9 microprocessor. The access to the configuration bitstream has been performed using the ZYNQ’s Processor Configuration Access Port (PCAP). Nevertheless, the flow presented in this article can be adapted to devices from other Xilinx families or vendors. The proposed approach has been fully tested and compared with specifically designed memory controllers. The results obtained in the experimental tests confirm that the proposed approach works properly without increasing the resource overhead but at a penalty in terms of processing time.  相似文献   

20.
This paper presents a field programmable gate array (FPGA) implementation of a three-layer perceptron using the few DSP blocks and few block RAMs (FDFM) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input–hidden–output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs and 9676 slices. It runs in 242.89 MHz clock frequency, and a single evaluation of 150 nodes perceptron can be performed 1.65 × 107 times per second.  相似文献   

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