本月推荐机型

家用初级型 机箱 电源 键盘 鼠标（３键带滚轴） ８１５主板灿坤 ＡＮＲＭｏｄｅｍＢａｒｅｂｏｎｅ内置声卡 １６００ 元 内置显卡 ５２ＸＣＤＲＯＭ １．４４Ｍ软驱ＣＰＵ赛扬 Ⅱ ７００ ６００元内存ＨＹ ６４Ｍ １７０元硬盘Ｍａｘｔｏｒ星钻２０Ｇ ７７０元显示器 ＳＯＣＯＳ １５” １０５０元总价 ４２３０元 游戏型ＣＰＵ雷鸟１Ｇ（１３３Ｍ外频）１２５０元主板捷波ＫＴ１３３Ａ８２０元内存 Ａｐａｃｅｒ １２８Ｍ ３２０元硬盘 Ｍａｘｔｏｒ星钻 ４０Ｇ １０５０元显示卡 ＡＴＩ Ｒａｄｅｏｎ ＬＥ ８８０元声卡 ＴＥＮＤＡ（４…     

金士顿内存与AMD亲密接触

在现今的内存市场上，可以说是风云变化，ＳＤＲＡＭ内存的价格屡创新低，目前１２８Ｍ的市场价格已经跌到１００多元，可以看出，内存厂商纷纷开始抛售手中的存货，积极调整产品线，迎接新内存时代，内存架构的一个转型期即将到来。业内人士把内存新架构接班人的目光都聚焦在ＲＡＭＢＵＳ和ＤＤＲ身上。ＲＡＭＢＵＳ是ＩＮＴＥＬ公司在相当一段时间内一直极力推广的新一代内存架构，而ＤＤＲ则是ＶＩＡ和ＡＭＤ鼓吹的一种替代ＳＤＲＡＭ的内存架构。 ＫＩＮＧＳＴＯＮ（金士顿）公司赵正刚先生认为，在今后的内存架构发展上，ＤＤＲ内存有…     

动起来—DIY您的内存BIOS设置

我们都知道合理的ＢＩＯＳ设置会给系统带来很大的性能提升,当然,如果对一些有关内存的ＢＩＯＳ选项进行准确合理的设置,将会大大的提升内存性能。下面我们一起来看看它到底是什么回事。系统平台主板：ＥＰＯＸ　　８ＫＨＡ（ＶＩＡ　ＫＴ２６６）ＣＰＵ：雷鸟１Ｇ风扇：大水牛Ｇ风神内存：Ａｐａｃｅｒ　１２８Ｍ　ＰＣ２１００　ＤＤＲ硬盘：星钻一代２０Ｇ光驱：酷客一族　５２Ｘ　ＣＤ－ＲＯＭ显卡：ＵＮＩＫＡ　小妖Ｇ　７６０Ｗ０显示器：大水牛１７英寸纯平显示器系统软件　　Ｗｉｎｄｏｗｓ　ＭＥ、ＳＩＳｏｆｔ　ｓａｎｄｒｏ　…     

2001年度上海城市信息化发展研究课题评标结果公布

资料：Ａｃｅｒ Ｖｅｒｉｔｏｎ ３２００,采用ＰＩＩＩ１ＧＨｚ处理器、１２８ＭＢ内存、１５英寸ＬＣＤ彩显、４０ＧＢ硬盘、５０速ＣＤ－ＲＯＭ、内建网卡声卡５６Ｋｂｐｓ Ｍｏｄｅｍ、Ｗｉｎｄｏｗｓ　Ｍｅ简体中文,报价１１３００元。Ａｃｅｒ Ｖｅｒｉｔｏｎ ３２００－Ｍ,采用ＰＩＩＩ１ＧＨｚ处理器、１２８ＭＢ内存、１５英寸ＬＣＤ彩星、４００ＧＢ硬盘、５０速ＣＤ－ＲＯＭ、内建网卡声卡５６Ｋｂｐｓ Ｍｏｄｅｍ、Ｌｉｎｕｘ简体中文,报价１０８００元。Ａｃｅｒ Ｖｅｒｉｔｏｎ ３２００－Ｃ,采用ＰＩＩＩ１ＧＨｚ处理器…     

用可编程控制器实现BEPC安全联锁系统——PLC在测控系统中…

本文介绍一种设计安全联锁系统的新方法，它的基本思想是采用可编程控制器（ＰＲＯＧＲＡＭＭＡＢＬＥ ＣＯＮＴＲＯＬＥＲ或ＰＲＯＧＲＡＭＭＡＢＬＥＬＯＧＩＣＣＯＮＴＲＯＬＬＥＲ－ＰＬＣ）替代过去的继电器和逻辑的控制，组成分布系统，以提高要靠性和可维护性，增加灵活性，缩短工期，节省人力和资金，一台多媒体ＩＢＭ－ＰＣ兼容机有作业上位机，监控整个系统。     

混合型符号几何规划的递归二次规划算法

混合型符号几何规划的递归二次规划算法张希，张可村（西安交通大学科学计算与应用软件系）ＡＳＵＣＣＥＳＳＩＶＥＱＵＡＤＲＡＴＩＣＰＲＯＧＲＡＭＭＩＮＧＡＬＧＯＲＩＴＨＭＦＯＲＭＩＸＥＤＳＩＧＮＯＭＩＡＬＧＥＯＭＥＴＲＩＣＰＲＯＧＲＡＭＭＩＮＧ￥Ｚｈａｎｇ...     

一种求解二次规划的简便方法

一种求解二次规划的简便方法刘萍，凌晓东（北京科技大学计算机系）（中信公司国际研究所）ＡＮＥＷＭＥＴＨＯＤＦＯＲＱＵＡＤＲＡＴＩＣＰＲＯＧＲＡＭＭＩＮＧ￥ＬｉｕＰｉｎｇ（ＤｅｐａｒｔｍｅｎｔｏｆＣｐｍｐｕｔｅｒＳｃｉｅｎｃｅ，ＵｎｉｖｅｒｓｉｔｙｏｆＳ...     

VIA KX133芯片主板剖析

现在市面上出现了很多ＶＩＡ（威盛）ＡＰＯＬＬＯ ＫＸ１３３ 芯片组的主板,ＡＰＯＬＬＯ ＫＸ１３３芯片组将为ＡＴＨＬＯＮ处理器提供比ＡＭＤ７５０芯片组更强大的兼容性和功能,它支持ＡＧＰ ４ｘ标准以及 ＰＣ１３３高速内存标准。本文将对采用ＫＸ１３３芯片组的主板进行分析和对比。 芯片组 ＫＸ１３３芯片组包括代号为ＶＴ８３７１的北桥芯片和ＶＴ８２Ｃ６８６Ａ“超级”南桥芯片,其结构图如下： ＶＴ８３７１支持 ＡＧＰ ４ｘ 高级图形技术标准,ＡＧＰ ４ｘ使图形的处理可以以 比此前的平台系统两倍 的速度与系统内存之间 进…     

用可编程控制器实现BEPC安全联锁系统——PLC在测控系统中的应用

本文介绍一种设计安全联锁系统的新方法，它的基本思想是采用可编程控制器（ＰＲＯＧＲＡＭＭＡＢＬＥＣＯＮ－ＴＲＯＬＬＥＲ或ＰＲＯＧＲＡＭＭＡＢＬＥＬＯＧＩＣＣＯＮＴＲＯＬＬＥＲ—ＰＬＣ）替代过去的继电器和专用逻辑的控制，组成分布式系统，以提高可靠性和可维护性，增加灵活性，缩短工期，节省人力和资金。一台多媒体ＩＢＭ－ＰＣ兼容机用作上位机，监控整个系统。     

梅捷SY-K7V DRAGON DDR主板

奔腾４风头正劲。但ＡＭＤ这边一直没有新产品推出,ＶＡ ＫＴ２６６和 ＤＤＲ内存的组合仍然是最能发挥Ａｔｈｌｏｎ性能的组合。在新一代ＶＩＡ ＫＴ２６６Ａ芯片组未推出之前各厂商仍然是将尽可能多的功能整合于一片主板之上。 梅捷 ＳＹ－Ｋ７Ｖ ＤＲＡＧＯＮ是 ＳＹ－Ｋ７Ｖ的功能增强版本。“ＤＲＡＧＯＮ”是“ＤＤＲ”．“ＲＡＩＤ”、“６－ｃｈａｎｎｅｌ　Ｈａｒｄｗａｒｅ　Ａｕｄｉｏ”　、“ＡＧＰ Ｐｒｏ”、“ＷＨＯＩＩ Ｏｖｅｒｃｌｏｃｋｉｎｇ”和“Ｎｅｔｗｏｒｋ １０／１００ＭｂｐｓＥｔｈｅｒｎｅｔ”６功能组合的…     

The abstract machine and implementation of parallel Parlog

This paper defines an abstract machine for implementing the logic language Parlog on shared memory multiprocessors. A process oriented execution model is introduced that specifies the mechanisms needed to support Parlog’s control facilities and then the abstract machine is presented, which specifies data structures, the instruction set and basic operations of the machine. An implementation of this abstract machine is then described and finally a brief summary of some performance results are given of benchmark programs executed on a shared memory multiprocessor.     

Linguistic extension of abstract machine modelling to aid software development

The traditional use of abstract machine models is to provide a conceptual framework for software design and to aid portability and machine independence. Access to the abstract machine model from the higher-level system on which it is based provides a powerful tool for software development. This paper describes a technique in which the higher-level system is interfaced to the underlying abstract machine, thus allowing use of the higher-level system to analyse and debug its own implementation. The application of this technique in the implementation of SL5 is given as an example. Experience with the use of the facility and a discussion of basic design considerations are included.     

An abstract machine for the implementation of PARLOG on uniprocessors

An abstract machine that supports the parallel logic programming language PARLOG is presented. This abstract machine is designed for the efficient execution of PARLOG on conventional uniprocessors and is thus named the Sequential PARLOG Machine (SPM). The machine’s architecture and instruction set are described and the principles of compilation of PARLOG programs to sequences of abstract machine instructions explained. The machine supports systems programming in PARLOG and in particular PARLOG’s powerful control metacall, which permits programs to initiate, monitor and control subcomputations.     

Towards the uniform implementation of declarative languages

Current implementation techniques for functional languages differ considerably from those for logic languages. This complicates the development of flexible and efficient abstract machines that can be used for the compilation of declarative languages combining concepts of functional and logic programming. We propose an abstract machine, called the JUMP-machine, which systematically integrates the operational concepts needed to implement the functional and logic programming paradigm. The use of a tagless representation for heap objects, which originates from the Spineless Tagless G-machine, supports the integration of different concepts. In this paper, we provide a functional logic kernel language and show how to translate it into the abstract machine language of the JUMP-machine. Furthermore, we define the operational semantics of the machine language formally and discuss the mapping of the abstract machine to concrete machine architectures. We tested the approach by writing a compiler for the functional logic language GTML. The obtained performance results indicate that the proposed method allows to implement functional logic languages efficiently.     

A conceptual approach for simulation software

This paper presents concepts and tools for simulation softwares specification. At an abstract level of specification, we define a simulation software as a couple (conceptual structure, abstract machine). The conceptual structure is a structured representation of the simulated system behaviour. The abstract machine is a set of abstract and general mechanisms able to carry out the management of a system defined through its conceptual schema. We focus in the paper on concepts for behaviour structuring and abstract machine tools.     

An intermediate language to define dynamic semantics

An instruction set is given for an abstract machine which uses a pushdown stack as its principal memory. The proposed instructions serve the similar purposes of (1) defining the dynamic semantics of programming languages by describing the operations of programs on the abstract machine and (2) describing an intermediate language to be used in compiling programming languages into machine language. It is shown how the intermediate language can be used in the translation of the programming languages ADA, FORTRAN and PASCAL into IBM 360 assembly language and advantages over other intermediate languages such as three-address code and P-code.     

An abstract machine theory for formal language parsers

Summary The usual data necessary for any abstract machine theory is given in categorical terminology. In these terms, an abstract machine theory for formal language parsers is developed, exposing the essential nature of any left-to-right parsing scheme. A weak classification of all parsers for a given language is developed and the usual notions of initial machine, reachable machine and minimal machine apply. Minimality is an extremely weak notion in this theory, although it is equivalent to a simple form of immediate error detection for parsers. Remarks on the construction of parsing procedures are given.Research supported in part by grant GJ-1171 from the National Science Foundation.     

A functional correspondence between call-by-need evaluators and lazy abstract machines

We bridge the gap between compositional evaluators and abstract machines for the lambda-calculus, using closure conversion, transformation into continuation-passing style, and defunctionalization of continuations. This article is a followup of our article at PPDP 2003, where we consider call by name and call by value. Here, however, we consider call by need.We derive a lazy abstract machine from an ordinary call-by-need evaluator that threads a heap of updatable cells. In this resulting abstract machine, the continuation fragment for updating a heap cell naturally appears as an ‘update marker’, an implementation technique that was invented for the Three Instruction Machine and subsequently used to construct lazy variants of Krivine's abstract machine. Tuning the evaluator leads to other implementation techniques such as unboxed values. The correctness of the resulting abstract machines is a corollary of the correctness of the original evaluators and of the program transformations used in the derivation.     

Concepts and realization of a high-performance data type architecture

Fifth generation computers are expected to capitalize on the dramatic progress of VLSI technology, in order to offer an improved performance/cost figure. An even more important requirement, however, is that they will support by architectural means the generation, execution, and maintenance of quality software, as a way out of the software crisis. One approach towards the design and implementation of quality software is programming with abstract data types, in connection with elaborate type consistency checking. The objection raised against the abstract data type based programming style is poor run time efficiency when such programs are executed on a conventional machine. In this paper adata type architecture is described that offers efficient and convenient mechanism for constructing arbitrary data structures and encapsulating them into abstract data types, thus avoiding the inefficiency penalty mentioned above. Through a process of hierarchical decomposition, user-defined abstract data types are mapped on representations given in terms of a basicstructured machine data type. This approach combines high performance with generality and completeness. The hardware structure of the data type architecture can be classified as a strongly coupled, asymmetric multicomputer system with hierarchical function distribution among the computers. The system includes a pipeline for numerical and nonnumerical operations, performed on the vector-structured basic machine data type in the SIMD mode of operation. Software reliability and data security is enhanced through elaborate run time consistency checking. The computer, which was designed and built at the Technical University of Berlin, has recently become operational. This paper outlines the operational principle, the mechanisms, and the hardware and software structure of this innovative, fifth generation computer architecture.This work was sponsored by the German Science Foundation under grant no. Gi 42/13.