片上网络容错技术研究

片上网络是一种全新的片上计算机体系结构,对片上网络的研究主要包括拓扑结构、路由算法、服务质量、交换机制、拥塞控制、能耗和容错等突出问题,其中对容错方法的研究一直是研究的重点。在软件改进和硬件改进方面,容错方法可以分为路由算法容错和路由器结构容错两类。分析当前已有容错方法的适用情况、实现原理和实现方法,并且分析其延迟、吞吐率、功耗等性能及其优缺点,对容错方法的现状进行剖析并且为容错方法的下一步研究提供研究方向。     

片上网络互连拓扑综述

随着器件、工艺和应用技术的不断发展,片上多处理器已经成为主流技术,而且片上多处理器的规模越来越大、片内集成的处理器核数目越来越多,用于片内处理器核及其它部件之间互连的片上网络逐渐成为影响片上多处理器性能的瓶颈之一。片上网络的拓扑结构定义网络内部结点的物理布局和互连方法,决定和影响片上网络的成本、延迟、吞吐率、面积、容错能力和功耗等,同时影响网络路由策略和网络芯片的布局布线方法,是片上网络研究中的关键之一。对比了不同片上网络的拓扑结构,分析了各种结构的性能,并对未来片上网络拓扑研究提出建议。     

二次改进遗传算法与3D NoC低功耗映射

随着集成电路技术的迅速发展,芯片的集成度不断提高,片上众多处理单元间的高效互连成为关键问题,因而相继出现了片上系统(system-on-chip,SoC)和二维片上网络(two-dimensional network-on-chip,2D NoC).当二维片上网络在多方面达到瓶颈时,三维片上网络(three-dimensional network-on-chip,3D NoC)应运而生.三维片上网络已引起学术界和产业界的高度重视,三维片上网络低功耗映射是其中的1个关键问题.之前的研究曾提出过一种基于改进遗传算法的3D NoC低功耗映射算法,并收到了良好的仿真效果.但当问题规模变大时,计算量随之增大、运行效率明显降低.针对这一问题,对3D NoC中面向功耗优化的二次改进遗传算法任务映射机制进行研究,提出了一种新的3D NoC低功耗映射算法,并对该映射算法进行了仿真实验.实验结果表明,在种群规模较大的条件下,该算法不仅能够继续降低功耗,而且能够大幅度地减少映射算法的运行时间.     

片上网络关键技术研究

半导体技术的快速发展以及芯片上系统应用复杂度的不断增长,使得片上互连结构的吞吐量、功耗、延迟以及时钟同步等问题更加复杂,出现了将通信机制与计算资源分离的片上网络.片上网络设计涉及从物理层到应用层诸多方面的问题.本文给出片上网络设计的一些关键技术:设计流程、拓扑结构、路由技术、交换技术、性能评估;并指出目前研究存在的问题和今后的研究方向.     

三维无线自组网络的成簇及自适应路由算法

针对三维无线自组织网络拓扑结构复杂导致的不易寻路的问题,提出成簇算法和基于部分超立方体网络结构(PCCN)的自适应路由算法.成簇算法考虑到节点疏密不均的情况,利用节点的空间密度分布将节点分割成候选簇,采用融合机制将候选簇构建成更均匀的簇结构.使用实际拓扑到虚拟拓扑的转化策略,在簇结构的基础上构建PCCN.PCCN作为虚拟拓扑结构,简化了实际网络拓扑,具有可扩展性、延伸性能好等优点.利用PCCN,对节点进行编号之后进行自适应路由.自适应路由算法包括簇内和簇间路由两种情况.算法分析及算例表明,PCCN简化了三维网络的拓扑结构,能够有效路由,为三维自组织网络的管理提出了新的方法和手段.     

片上网络映射优化问题研究与进展

映射优化问题是片上网络关键技术之一,其模型的建立及求解影响着片上网络性能。映射问题被证明是NP问题,传统求解具有一定的难度,多采用启发式算法完成。为了解当前映射优化问题研究现状及发展前景,针对片上网络IP核到网络节点的匹配优化问题进行建模和分类,并对当前研究中的一些典型映射算法在目标、约束条件、性能、采用拓扑结构等方面进行对比分析,最后给出片上网络中映射优化问题未来的研究方向。     

混合无线三维片网中无线路由节点分布研究

传统的片上网络都是采用金属链路连接各个路由节点,芯片上IP核的增多一方面导致了布线复杂度的增加,另一方面也导致了片上网络传输延迟和功耗的增加。由于片上微型天线的成功研制,芯片内的无线通信得以实现。无线通信具有高带宽、低延迟、低功耗的特点,使得无线片上网络(WNoC)成为传统片上网络最理想的替代方案,可以显著提高系统的性能。针对传统大规模片上网络(NoC)远距离核间多跳通信所带来的高能耗与延时问题,提出了一种8×8×4的三维混合无线片上网络架构以及针对该架构的路由算法。此外,对在混合型无线片上网络的拓扑设计中所遇到的无线节点和无线链路放置等问题进行了讨论。仿真结果表明,将无线节点放在第0层和第3层所得到的性能最好,且该拓扑结构与传统片上网络结构相比,在网络平均延迟以及网络总功耗方面取得了很大的提升。     

NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

Globe:低延时可扩展的P2P网络拓扑框架

该文将图论方法运用于计算机网络研究,提出了一种低延时、结构化、可扩展的P2P网络拓扑框架──Globe,在尽量少增加节点邻居数的前提下,通过严格控制和优化节点之间的邻接关系来构造分层次的拓扑结构,有效地减小了网络的平均距离,实现了分组的低延时转发;并基于该拓扑框架设计出了一种快速的路由算法,这一网络框架和路由算法在P2P网络上的资源查找和数据交换等方面都具有实际的意义。     

基于前缀的片上网络容错源路由算法

为克服片上网络链路永久性错误带来的路由问题,提出一种基于前缀的片上网络容错源路由算法PFTSR。该算法适用于二维mesh片上网络,采用预测路径并根据反馈信息调整路径的方法进行路由探测。在仿真平台NIRGAM上进行仿真,实验结果表明,与传统片上网络容错源路由算法SRN相比,PFTSR极大降低了片上系统的功耗,并且在大多数情况下能减少探测到第一条路径的时间。     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.     

A survey of routing algorithm for mesh Network-on-Chip

With the rapid development of semiconductor industry, the number of cores integrated on chip increases quickly, which brings tough challenges such as bandwidth, scalability and power into on-chip interconnection. Under such background, Network-on-Chip (NoC) is proposed and gradually replacing the traditional on-chip interconnections such as sharing bus and crossbar. For the convenience of physical layout, mesh is the most used topology in NoC design. Routing algorithm, which decides the paths of packets, has significant impact on the latency and throughput of network. Thus routing algorithm plays a vital role in a wellperformed network. This study mainly focuses on the routing algorithms of mesh NoC. By whether taking network information into consideration in routing decision, routing algorithms of NoC can be roughly classified into oblivious routing and adaptive routing. Oblivious routing costs less without adaptiveness while adaptive routing is on the contrary. To combine the advantages of oblivious and adaptive routing algorithm, half-adaptive algorithms were proposed. In this paper, the concepts, taxonomy and features of routing algorithms of NoC are introduced. Then the importance of routing algorithms in mesh NoC is highlighted, and representative routing algorithms with respective features are reviewed and summarized. Finally, we try to shed light upon the future work of NoC routing algorithms.     

基于拥塞控制的片上网络多播路由算法

为了满足片上网络日益丰富的应用要求,多播路由机制被应用到片上网络,以弥补传统单播通信方式的不足。以Mesh和Torus类的片上网络为例,分析了基于路径的3种多播路由算法(即XY路由、UpDown路由和SubPartition路由算法),并研究了相应的拥塞控制策略。通过模拟实验表明,多播较单播通信具有更小的平均传输延时和更高的网络吞吐量,且负载分配均匀;特别是SubPartition路由算法随着规模增大效果更加明显;提出的多播拥塞控制机制,能更有效地利用多播通信,提高片上网络的性能。     

基于3D Mesh结构的一种静态路由算法

3D NoC在同构多核系统中相比2D NoC具有更为优越的性能.本文在研究3D Mesh结构的基础上,对拓扑结构中的平均延时和理想吞吐量进行了理论上的评估,并提出了一种基于3D Mesh的新的静态路由算法,最后运用NS2网络仿真软件对其进行仿真和比较.实验结果显示,新的路由算法可以有效地提高吞吐量,并在大规模数据传输时...     

一种用于片上网络的拥塞感知哈密尔顿最短路径路由算法

类脑处理器能够支持多种脉冲神经网络SNN的部署来完成多种任务。片上网络NoC能够用较少的资源和功耗解决片上复杂的互连通信问题。现有的类脑处理器多采用片上网络来连接多个神经元核,以支持神经元之间的通信。SNN在时间步内瞬时突发的通信会在短时间内产生大量的脉冲报文。在这种通信行为下,片上网络会在短时间内达到饱和,造成网络拥塞。片上网络中非拥塞感知路由算法会进一步加剧网络拥塞状态,如何在每一个时间步内有效处理这些数据包,从而降低网络延迟,提高吞吐率,成为了目前需要解决的问题。首先对SNN的瞬时猝发通信特性进行了分析;然后提出一种拥塞感知的哈密尔顿路径路由算法,以降低NoC平均延迟和提高吞吐率;最后,使用Verilog HDL实现该路由算法,并通过模拟仿真进行性能评估。在网络规模为16×16的2D Mesh结构的片上网络中,相对于没有拥塞感知的路由算法,在数量猝发模式和概率猝发模式下,所提出的拥塞感知路由算法的NoC平均延迟分别降低了13.9%和15.9%;吞吐率分别提高了21.6%和16.8%。     

Performance-driven assignment and mapping for reliable networks-on-chips

Network-on-chip （NoC） communication architectures present promising solutions for scalable communication requests in large system-on-chip （SoC） designs. Intellectual property （IP） core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the draw-backs of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite （E3S）. Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.     

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology cannot ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.     

NoC低功耗技术研究综述

当前在高性能SoC设计中,功耗约束已成为NoC设计所面临的重要问题。本文着重阐述了NoC低功耗优化技术的相关内容,在分析现有NoC模拟器和功耗模型的基础上,从物理逻辑设计、软件编译优化、网络拓扑结构低功耗映射等方面评述了当前NoC低功耗关键技术。最后,对未来NoC低功耗技术研究的方向做出了预测。     

一种二维片上网络路由器的设计实现

片上网络(Network on Chip, NoC)作为解决众核芯片互连的主流方案,其性能很大程度上取决于网络的拓扑结构。而网络拓扑结构的效能受到网络路由器的直接影响。因此,基于特定拓扑结构的路由器设计实现具有非常重要的研究意义。因此将XY路由算法应用于路由器节点中,设计了基于2D Mesh拓扑结构、轮询仲裁机制与虫孔交换流控的片上网络路由器,并使用Modelsim对路由器进行了功能验证。实验结果表明,设计的路由器能满足微片数据的处理,能够正确的收发数据包。