基于SoC的小型集成化视频采集处理系统研究

由于传统视频采集和处理系统很难解决小体积、低功耗与高数据带宽和处理速度之间的矛盾,同时针对智能武器装备、工业自动化生产等领域对视频采集与处理系统小型化、集成化发展需求,基于Xilinx公司高性能Zynq-7000系列SoC芯片,搭建了一种小型化、集成化、通用化视频采集处理平台系统。通过充分发挥SoC芯片集成ARM处理器软件可编程和FPGA硬件可编程优势,提出了利用HLS工具将图像预处理算法快速打包生成IP核,在FPGA中实现图像算法硬件加速的设计方法,不仅保证了视频采集和处理的实时性,而且实现了视频处理设备小型化、集成化、低功耗设计。对系统软硬件设计和各组成部分原理进行了介绍,并以Sobel边缘检测算子为实例,对系统功能和性能与传统处理方法进行了对比测试,验证了系统的有效性。     

FPGA implementation of reversible watermarking in digital images using reversible contrast mapping

Reversible contrast mapping (RCM) and its various modified versions are used extensively in reversible watermarking (RW) to embed secret information into the digital contents. RCM based RW accomplishes a simple integer transform applied on pair of pixels and their least significant bits (LSB) are used for data embedding. It is perfectly invertible even if the LSBs of the transformed pixels are lost during data embedding. RCM offers high embedding rate at relatively low visual distortion (embedding distortion). Moreover, low computation cost and ease of hardware realization make it attractive for real-time implementation. To this aim, this paper proposes a field programmable gate array (FPGA) based very large scale integration (VLSI) architecture of RCM-RW algorithm for digital images that can serve the purpose of media authentication in real-time environment. Two architectures, one for block size (8 × 8) and the other one for (32 × 32) block are developed. The proposed architecture allows a 6-stage pipelining technique to speed up the circuit operation. For a cover image of block size (32 × 32), the proposed architecture requires 9881 slices, 9347 slice flip-flops, 11291 number 4-input LUTs, 3 BRAMs and a data rate of 1.0395 Mbps at an operating frequency as high as 98.76 MHz.     

An FPGA multiprocessor architecture for Bayesian online change point detection using stochastic computation

In this paper we report on an event-based stochastic architecture for the Adams/McKay Bayesian Online Change Point Detection algorithm (BOCPD) [1]. In the stochastic computational structures, probabilities are represented natively as stochastic events and computation is carried out directly with these probabilities and not probability density functions. A fully programmable BOCPD processor is synthesized in VHDL. The BOCPD algorithm with on-line learning, to perform foreground/background image segmentation with online learning. Running on a single Kintex 7 FPGA (Opal Kelly XEM7350-K410T) the architecture is capable of real-time processing a 160 × 120 pixels image, at 10 frames per second.     

Fast structural similarity index algorithm

The development of real-time image and video quality assessment algorithms is an important direction on which little research has focused. Towards this end, we present a design of real-time implementable full-reference image/video quality algorithms that are based on the Structural SIMilarity (SSIM) index and multi-scale SSIM (MS-SSIM) index. The proposed algorithms, which modify SSIM/MS-SSIM to achieve speed of execution, were tested on the LIVE Image Quality Database and LIVE Video Quality Database. The experimental results show that the performance of the new, fast algorithms is commensurate with that of SSIM and MS-SSIM, but with much lower computational complexity. Indeed, the proposed Fast MS-SSIM algorithm is 10 times faster (lower complexity) than the MS-SSIM algorithm, while the proposed Fast SSIM is 2.68 times faster than SSIM without parallel computing optimization.     

Multimodal registration of visible,SWIR and LWIR images in a distributed smart camera system

We present a multimodal registration algorithm between images in the visible, short-wave infrared and long-wave infrared spectra. The algorithm works with two reference-objective image pairs and operates in two stages: (1) A calibration phase between static frames to estimate the transformation parameters using histogram of oriented gradients and the Chi-square distance; (2) a frame-by-frame mapping with these parameters using a projective transformation and a bilinear interpolation to map the objective video stream to the coordinate system of the reference video stream. We present a distributed heterogeneous architecture that combines a programmable processor core and a custom hardware accelerator for each node. The software performs the calibration phase, whereas the hardware computes the frame-by-frame mapping. We implemented our design using a Xilinx Zynq XC7Z020 system-on-a-chip for each node. The prototype uses 2.38W of power, 25% of the logic resources and 65% of the available on-chip memory per node. Running at 100MHz, the core can register 640  ×  512-pixel frames in 4ms after initial calibration, which allows our module to operate at up to 250 frames per second.     

基于FPGA的运动目标检测系统

视频图像处理要求高速运算能力,在处理技术不断提高和算法复杂度不断提升的情况下,并行处理的可编程逻辑器件的高速运算能力和可重复执行多任务的特性在视频图像处理领域得到了极大的发挥。与传统的串行处理DSP芯片为核心器件的视频图像处理方案相比,单片FPGA芯片和嵌入其内部酌NiosII软核处理器不仅能够达到运算速度的要求,而且成本更低、设计更简单。系统由I2C模块、视频译码模块、存储模块和检测模块组成,模块之间由Avalon总线链接。系统基于QuartusⅡ、MATLAB和ModelSim软件工具设计与仿真．实验结果表明能够达到预期的要求。     

基于FPGA的HEVC后处理CNN硬件加速器研究

针对高效视频编解码标准中后处理CNN算法在通用平台运行时产生的高延时缺点,提出一种基于现场可编程逻辑门阵列（FPGA）的后处理卷积神经网络硬件并行架构。提出的并行架构通过改进输入与输出缓冲的数据并发过程,调整卷积模块整体并行度,加快模块硬件流水。实验结果表明,基于本文所提出的并行架构设计的CNN硬件加速器在Xilinx ZCU102上处理分辨率为176×144视频流,计算性能相当于每秒360.5 GFLOPS,计算速度可满足81.01 FPS,相比时钟频率4 GHz的Intel i7-4790K,计算速度加快了76.67倍,相比NVIDIA GeForce GTX 750Ti加速了32.50倍。在计算能效比方面,本文后处理CNN加速器功耗为12.095 J,能效比是Intel i7-4790K的512.90倍,是NVIDIA GeForce GTX 750Ti的125.78倍。     

基于FPGA的视频图像高速处理技术——在钢轨动态检测中的应用

高速图像处理可用软件和硬件两种方案实现。软件方案成本低,灵活,但速度慢;硬件方案速度高,不够灵活且成本高。现场可编程门阵列(FPGA)正好能解决这一矛盾。介绍了一种基于FPGA的视频图像高速处理技术,它被成功地用于钢轨断面图像的实时动态监测系统中。该系统采用了投票表决算法,用VHDL语言(超高速集成电路硬件描述语言)编程,采用多语言协同仿真技术(FLI)。结果表明,该系统充分发挥了FPGA器件的并行特性,显著提高了图像处理速度,达到了动态监测的实时性要求。     

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

The advent of the Internet of Things has motivated the use of Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications - namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks.     

滑动DCT-LMS自适应算法研究与FPGA实现

研究一种改进的低复杂度复数滑动离散余弦变换(DCT)最小均方(LMS)自适应算法,并设计该算法的FPGA实现结构。在常规LMS算法的输入端前添加改进的滑动DCT,降低输入信号之间的关联性,提高自适应算法收敛速度。改进的滑动DCT算法针对硬件实现进行了优化,提高其在硬件实现中稳定性和精度。给出算法在FPGA实现框图、结果和Matlab仿真结果的对比,以及算法在FPGA中的资源使用。算法已经在实际工程中应用,效果远优于常规LMS自适应算法。     

FPGA implementation of full-search vector quantization based on partial distance search

This paper presents a novel algorithm for field programmable gate array (FPGA) realization of vector quantizer (VQ) encoders using partial distance search (PDS). In most applications, the PDS is adopted as a software approach for attaining moderate codeword search acceleration. In this paper, a novel PDS algorithm well suited for hardware realization is proposed. The algorithm employs subspace search, bitplane reduction, and multiple-coefficient accumulation techniques for the effective reduction of the area complexity and computation latency. Concurrent encoding of different input vectors for further computation acceleration is also allowed by the employment of multiple-module PDS. The proposed implementation has been embedded in a softcore CPU for physical performance measurement. Experimental results show that the implementation provides a cost-effective solution to the FPGA realization of VQ encoding systems where both high throughput and high fidelity are desired.     

Exponential fractional cat swarm optimization for video steganography

In this paper, an effective method named Exponential Fractional-Cat Swarm Optimization (Exponential Fractional-CSO) along with multi-objective cost function is proposed. The proposed method is designed by integrating the CSO with the fractional concept based on the Exponential parameters. Initially, an input video is selected from the database from which frames are generated. Key frames are chosen among the frames using the contourlet transform and Structural Similarity Index Measure (SSIM). Regions are formed on the selected key frames through the help of grid lines. Once the regions are formed, optimal regions are ascertained with the help of the proposed optimization algorithm along with multi-objective cost functions to hide the secret data. During the embedding process, the secret data is hidden in the optimal region using the lifting wavelet transform (LWT). The embedded video is then transmitted through the network to reach its intended receiver. The experimental results reveal that the proposed Exponential Fractional-CSO obtained a maximal correlation of 0.9931 by considering the frames, maximal Peak Signal-to-Noise Ratio (PSNR) of 89.70 dB and MSE of 0.00006 respectively. Hence, the proposed method shows greater effectiveness of hiding the secret data in the video sequence along with data security.

     

Efficient hardware architectures for computation of image moments

Geometric moments are used in numerous image analysis tasks. While several approaches have been proposed, real-time computation is still inefficient. In this paper, a mathematical formulation of the relationship of the all-pole filter output to the geometric moments is discussed. Using this formulation, architectures for implementing in hardware geometric moments of 1, 2 or 3D objects are proposed. Four implementations are programmed in field programmable logic devices (FPGA) devices with typical clock frequencies of 40 MHz. The speed of these devices is adequate for real-time applications, and they can be used to extract local as well as global geometric moments.     

三维扫描仪中人头轮廓线提取方法及实现

为解决三维扫描仪的实时性,文章提出了以FPGA处理器与PC主机交互式共同完成提取轮廓线的快速算法。该算法由两个阶段组成:第一阶段由主机计算背景与目标的分割阈值。第二阶段由FPGA处理器实时检测轮廓线位置信息。该快速算法具有计算简单、实现速度快等优点,并且减少了传输与存储的数据量,减轻了后面主机计算工作量。同时,省掉了昂贵的图像采集压缩卡与高速硬盘,降低了成本。可重构FPGA处理器设计成流水线结构,对每个像素的平均处理时间控制在70ns以内。仿真与综合结果表明:从一帧720576标准PAL制视频图像中提取轮廓线信息可在40ms内实时完成。     

Video image scaling technology based on adaptive interpolation algorithm and TTS FPGA implementation

With the rapid development of digital multimedia terminals, the scaling of video images has solved the needs of high-end displays for low-resolution signals and high-definition signals displayed by low-end displays. The main purpose of this article is to convert the input video image signal into a video image signal with the required resolution through video image scaling. This article mainly studies various image scaling algorithms, analyzes their advantages and disadvantages, and adopts a top-down design method to implement FPGA video scaling design and verify the correctness of the results. This article introduces various traditional image interpolation algorithms. On the basis of comparing the subjective and objective quality of the image after the summation of various algorithms, the fuzzy interpolation algorithm is used to zoom the video image. In FPGA design, horizontal scaling and vertical scaling are handled separately, which reduces the computational complexity of image upgrades and facilitates control logic and specific implementation. The experimental results of this paper show that the maximum working frequency that the designed image scaling unit can reach is 153.12 MHz, which can process 1080p video signals in real time. Video image scaling technology has broad market prospects.     

基于FPGA的视频采集及转换系统设计

基于数字图像处理技术和FPGA（现场可编程门阵列）技术,针对高精度单色CCD视频传感器1010_M的输出规范,结合高速视频接口标准的需求,设计并实现了一种视频采集及转换系统。系统重点介绍了视频采集及转换系统硬件电路结构,软件设计流程,主要相关电路设计和FPGA逻辑设计,并给出测试结果。     

数字图像处理算法评估系统的硬件设计

为了能对不同的数字图像处理算法进行评估,采用了USB2．0总线技术传送数字图象数据到数字图像处理系统,在硬件设计上采用DSP＋FPGA来完成图像处理任务。整个系统具有处理能力强,重现性好,能完成各种图像处理算法评估。     

Design of parallel conversion multichannel analog to digital converter for scan time reduction of programmable logic controller using FPGA

The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital input it scans, complication in ladder diagram and the time to store the ladder diagram outputs in memory. Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into digital. The two facts that limit the conversion speed is that the processor used for analog signal scanning can process only one channel at a time and the multichannel analog to digital converter (ADC) has digital output for only one channel. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals into digital and storage of digital data in block RAM. The proposed design discusses the design of multichannel ADC using FPGA. The simulation result shows that the conversion time of ‘n’ channel ADC is 13.17 μs. This increases the PLC execution speed.     

基于特征跟踪和网格路径运动的视频稳像算法

针对手持移动设备拍摄的抖动视频问题,提出了一种基于特征跟踪和网格路径运动的视频稳像算法。通过SIFT算法提取视频帧的特征点,采用KLT算法追踪特征点,利用RANSAC算法估计相邻帧间的仿射变换矩阵,将视频帧划分为均匀的网格,计算视频的运动轨迹,再通过极小化能量函数优化平滑多条网格路径。最后由原相机路径与平滑相机路径的关系,计算相邻帧间的补偿矩阵,利用补偿矩阵对每一帧进行几何变换,从而得到稳定的视频。实验表明,该算法在手持移动设备拍摄的抖动视频中有较好的结果,其中稳像后视频的PSNR平均值相比原抖动视频PSNR值大约提升了11.2 dB。与捆绑相机路径方法相比约提升了2.3 dB。图像间的结构相似性SSIM平均值大约提升了59%,与捆绑相机路径方法相比约提升了3.3%。     

基于FPGA的红外焦平面阵列图像采集及处理系统设计

介绍了一种基于FPGA的图像采集及处理系统实现方案,采用Altera公司的EP2C35系列现场可编程门阵列FPGA作为控制核心,完成了图像采集、存储、预处理及下位机实时视频合成、显示等功能;简介了各功能模块的实现方案,给出了软硬件实现要点及实验结果,系统末端Camera Link协议接口配合PCI图像采集卡将采集处理后的信号传送至上位机;在上位机端的Sapera CamExpert用户界面中以grab连续采集或snap单帧采集模式即可捕获下位机端送来的图像信号,从而实现了高速实时图像采集及处理。