声全息重构卷积计算中混迭问题的研究

分析了实空间离散格林函数的特点和平面声全息重构卷积计算的特殊性，推导了在重构条件下二维循环卷积与重构卷积的关系。理论上证明了在全息重构中将二维全息声压序列补零使其成为原序列长度的两倍，而二维格林函数序列无需进行补零处理仍可由二维离散傅氏变换准确地得到全息重构卷积结果，而不会产生循环卷积中的混迭现象，即不存在所谓的重构“卷绕”误差。同时还证明了实空间格林函数的取值不确定性不会影响重构结果，并通过仿真算例进行了验证。     

二维阵列型可重构计算的层次型参数模型

建立可重构计算的高层次结构模型是可重构计算设计空间搜索的一项研究内容。该文提出一种适用于二维阵列型可重构计算的层次型参数模型。该模型分为顶层描述结构、功能模块描述结构、单元描述结构和功能描述结构4个层次。忽略具体结构细节,在较高的抽象层次描述可重构计算的结构特征。应用实例表明,该模型具有较好的灵活性和层次性,能够描述不同架构的二维阵列型可重构计算。     

可重构计算处理器技术

本文首先分别分析了基于指令流驱动和基于数据流驱动的传统计算技术所面临的问题,并介绍了可重构计算处理器的发展趋势;接着,讨论了可重构计算处理器的硬件架构和编译技术,重点分析了其在软硬件架构及系统应用上所面临的挑战;然后,介绍了所设计的REMUS(REconfigurable MUltimedia System)可重构计算媒体处理器及其相应的集成开发工具;最后,展望了面向通用计算的可重构技术的发展前景.     

图像处理系统中的新型动态重构技术

阐述了一种新型动态结构可重构技术及其在分布式图像处理系统中的应用。以并行处理中的流水线技术和空间并行技术为基础，结合二者的优点提出一种可动态重构的结构模型，通过决策代价函数进行最优判决，将分解后算法任务最佳地映射到体系结构中去，在时间维和空间维上提高整个系统的实时并行处理性能。在实际环境中验证了该动态技术的正确性和优越性。     

基于多项式变换的二维整型离散余弦变换快速算法

提出了一种基于多项式变换的二维整型离散余弦变换（DCT）快速算法，利用多项式变换将二维DCT变换的计算转化为一系列一维DCT变换及其变换系数的求和运算，减少了乘法和加法的计算量；利用提升矩阵，实现了整型DCT变换，进一步提高了运算效率的同时，使信号可精确重构。     

FPGA动态可重构理论及其研究进展

近年来,随着微电子技术和计算机技术的发展,尤其是大规模现场可编程门阵列FPGA的出现,实时电路重构技术逐渐成为国际学术界的研究热点;基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用;文章介绍了基于FP-GA动态可重构技术的原理、分类,重点讨论了动态可重构的实现方法及两种技术,并给出了系统重构设计的流程,同时,介绍了基于FPGA动态可重构技术已取得的成功应用,最后展望了FPGA动态可重构技术的发展前景,并指出了有待解决的问题.     

基于Toeplitz矩阵重构的无人机相干信号DOA估计算法

针对实时监管无人机的需求设计了基于Toeplitz矩阵重构的二维相干DOA 估计算法,建立了虚拟线阵模型来 接收无人机相干信号,通过对协方差矩阵进行矩阵重构来实现信号解相干,构建了Toeplitz矩阵,通过计算空间谱实现对无人 机信号的二维DOA 估计,仿真分析表明本文方法的DOA 估计准确率较高,性能较好。     

可重构多核片上系统体系结构综述

可重构片上多核系统利用不同粒度、不同耦合度的可重构资源,充分开发资源的并行性,兼顾硬件计算的高性能及软件实现的灵活性,且复用特性使其具备开发设计成本降低、产品面市时间缩短的优势。介绍可重构计算系统概念及其分类,从系统级层面回顾可重构多核片上系统体系结构的研究进展,讨论未来的研究趋势及需要关注的关键问题。     

面向多媒体的并行加速系统中可重构网络结构设计

本文讨论了面向多媒体数据处理的并行加速系统硬件平台的设计，采用数字信号处理芯片作为基本的工作单元，提出了一种基于ｍｅｓｈ阵列的可重构网络结构设计及其控制方法，并对其性能进行了定性分析。     

基于视频六维分布模型的运动对象分割

视频运动对象检测是智能安全监控的基本问题。考虑视频的时间空间分布规律，该文构造了视频六维分布模型以进行运动对象分割。在时间维上利用在线高斯混合模型对背景进行更新，并且计算像素颜色差异。在空间维上利用纹理特征描述像素点之间结构关系，提高了对光线变化和阴影等环境变化的抗干扰能力。实验结果表明该算法是实用有效的。     

异构重构计算系统应用任务调度的性能分析

异构重构计算是目前高性能计算的研究热点.由于应用任务的异构性,以及体系结构的可重构性,导致异构重构计算的性能分析非常困难,现有的并行计算性能分析方法不再适用.本文提出一种基于应用任务调度的性能分析方法,该方法以异构重构计算系统模型和应用任务模型为基础,利用异构匹配、重构耦合矩阵,实现应用任务和处理部件的优化选择和耦合匹配,通过调度算法求出应用任务在异构重构计算系统中的完成时间,并进行了实例分析.     

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts.     

An improved constant-time algorithm for computing the Radon andHough transforms on a reconfigurable mesh

The Hough transform is an important problem in image processing and computer vision. An efficient algorithm for computing the Hough transform has been proposed on a reconfigurable array by Kao et al. (1995). For a problem with an √N×√N image and an n×n parameter space, the algorithm runs in a constant time on a three-dimensional (3-D) n×n×N reconfigurable mesh where the data bus is N¹c/-bit wide. To our best knowledge, this is the most efficient constant-time algorithm for computing the Hough transform on a reconfigurable mesh. In this paper, an improved Hough transform algorithm on a reconfigurable mesh is proposed. For the same problem, our algorithm runs in constant time on a 3-D n*n×n×√n√n reconfigurable mesh, where the data bus is only log N-bit wide. In most practical situations, n=O(√N). Hence, our algorithm requires much less VLSI area to accomplish the same task. In addition, our algorithm can compute the Radon transform (a generalized Hough transform) in O(1) time on the same model, whereas the algorithm in the above paper cannot be adapted to computing Radon transform easily     

Deriving algorithms on reconfigurable networks based on function decomposition

In this paper, a new approach, which is based on function decomposition, is proposed for deriving algorithms on processor arrays with reconfigurable bus systems. The effectiveness of this approach is shown through some important applications. They include computing the logical exclusive-OR of n bits, summing n bits, summing n m-bit binary integers, and multiplying two n-bit binary integers. All these applications are solved in O(1) time.     

面向国产CPU的可重构计算系统设计及性能探究

为了提升国产平台的计算性能,采用国产CPU+FPGA的异构架构,设计了基于国产CPU的可重构计算系统。该系统包括基于国产CPU的主机单元和FPGA可重构加速单元,主机单元负责逻辑判断与管理调度等任务,FPGA负责对计算密集型任务进行加速,并采用OpenCL框架模型进行编程,以缩短FPGA的开发周期。为了验证该系统的性能,采用AES加密算法来测试该系统的计算性能,通过对不同长度的明文进行AES加密测试,并与CPU串行处理结果进行对比,得出：相比于单核FT-1500A CPU串行加密方式,采用可重构计算系统并行加密能够获得120多倍的加速比,且此加速比会随着明文长度的增加而成非线性增大。实验结果表明：基于国产CPU的可重构计算系统能够大幅提升国产平台的计算性能。     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Computing the Duquenne–Guigues basis: an algorithm for choosing the order

This paper presents an algorithm for choosing the order in which pseudo-intents are enumerated when computing the Duquenne–Guigues basis of a formal context. Sets are constructed through the use of a spanning tree to ensure they are all found once. The time and space complexities of the algorithm are empirically evaluated using, respectively, the number of logical closures and the number of sets in memory as measures. It is found that only the space complexity depends on the enumeration order.     

基于随机Petri网的可重构核心单元分析

利用随机Petri网对可重构核心单元进行建模,对其可达性、有界性、安全性等结构特性进行逻辑正确性验证,并对其稳态概率、变迁概率、吞吐量等性能特性进行数量化求解。在好、中、差3种速率情况下讨论动态重构对计算任务完成时间的影响,分析结果表明,可重构核心单元的动态重构响应越及时,其任务处理时间就越少。     

Multi-level reconfigurable architectures in the switch model

In this paper, we propose a concept for multi-level reconfigurable architectures with more than two levels of reconfiguration, and study these architectures theoretically and experimentally. The proposed architectures are extensions of 2-level reconfigurable architectures where the reconfiguration operations on the lowest level correspond to the reconfiguration operations of standard 1-level reconfigurable architectures, and the reconfigurable units are simple switches. It is shown that finding an optimal number of reconfiguration levels and a corresponding reconfiguration scheme that minimizes the number of reconfiguration bits for a given algorithm can be done in polynomial time. But finding the optimal number of reconfiguration levels is NP-hard for heterogeneous multi-level architectures, where the number of reconfiguration levels varies for the different reconfigurable units. Experimental results for different test applications show that 3–4 reconfiguration levels are optimal with respect to the number of reconfiguration bits needed. The number of reconfiguration bits is reduced by 35–86% compared to 1-level reconfiguration and by 8–34% compared to 2-level reconfiguration. The heterogeneous architecture reduces the number of necessary reconfiguration bits by additional 1–5% and also needs less SRAM cells.     

高性能计算中应用驱动的多DSP处理器阵列研究*

数字信号处理（DSP）芯片是一种特别适合于进行数字信号处理运算的微处理器,高性能计算由于大数字运算量和高速处理的要求,因而非常适合于DSP的应用。本文针对工业CT图像的三维重建这一典型应用,分析了DSP在高性能计算中的应用特点、方式和效果,提出了一种动态可重构的多DSP处理器阵列的设计方法。最后通过软硬件仿真验证了DSP在高性能计算中的性能和多DSP设计方案的可行性。