面向机器人装配设计与规划的集成框架

本文针对面向机器人装配的产品设计与装配规划中的关键问题,分析实际产品设计与 装配规划的一般过程,提出了将面向机器人装配的产品设计与装配规划进行系统集成的框架 ,并对系统的各个模块的功能和实现作了研究探讨,通过在工程实践中的应用验证了其正确 性和有效性．     

机器人化装配

机器人化装配已成为机器人研究与应用的一个热点．１０年前，文献［１］已就此作了综述，本文旨在补充这以后的新成果．首先，简单介绍各种装配机器人和装配设计方法．然后对手腕的各种高精度插轴入孔措施，尤其是高速装配控制进行了详述．文末提出了一些研究方向．     

机器人力装配操作的顺应综合与实验验证

本文提出并实现了一种机器人装配顺应综合方法．装配操作过程可以表示为一列离散 的几何接触状态的改变和转移．通过对不确定性下所有机器人形位进行仿真,得到每一接触 形式对应的静态接触力特征．由对基本接触元的分析,求解实现接触状态转移的机器人运动 方向,构成顺应的力 错误修复运动方向映射,为规划的装配运动实现提供顺应．并在PUMA 562机器人上完成了一类简单装配实验对本文的方法进行了验证．     

一种基于机器人的航天器大型部件自主装配方法

航天器大型部件在狭小空间中装配存在着视野受限、目标位置不可见等问题,传统的吊装方法无法精确调整位姿、磕碰风险极高．本文提出一种基于双目视觉定位的机器人辅助装配路径规划方法．该方法以航天器、待安装部件以及机器人等装配要素的3维模型为基础,采用双目视觉系统对航天器上安装位置的几何特征进行精确定位．利用测量结果确定机器人和航天器之间的相对位姿关系,进而构建航天器装配现场的虚拟环境,识别装配过程中的几何约束,然后利用轴对齐包围盒方法进行碰撞检测,采用随机路图法规划出一条无干涉的装配路径,最后利用离线编程技术生成机器人可执行的装配序列．以某型号航天器激光测高仪为对象开展装配试验,完成了大型部件在狭小凹舱内的无磕碰安装．结果表明该方法可以实现对螺纹孔精准定位,快速规划出无干涉装配路径,能够控制机器人安全、高效完成大型部件在狭小空间下的安装作业．     

基于约束关系的装配规划

本文为柔性装配系统(FAS)或机器人装配单元提出一种新的装配规划表示方法,它是在用有向无环图表示装配操作约束关系的基础上,用树结构来表示装配规划的表示方法。本文给出表示方法的形式化描述和在此表示上的线性装配规划的生成算法。     

虚拟触觉传感器的仿真模型研究

本文根据真实触觉传感器的原理,对虚拟触觉传感器的仿真模型进行了研究,以便 在机器人手抓拾取操作中揭示与材料特性相关的触觉信息瞬态特性,进而为在虚拟环境中从 事基于传感信息的机器人柔性操作、精密装配操作等提供良好的研究平台．     

装配序列规划研究综述

装配序列规划是机器人智能装配中的一项重要研究课题，也是ＣＡＤ／ＣＡＭ以及ＣＩＭＳ研究的一个重要组成部分，涉及计算机，人工智能，自动化，机器人和机械工程等领域，本文对机械装配序列规划研究的历史和技术现状进行了综述。     

模块化机器人拓扑重构规划研究

模块化可重构机器人由若干个相同的机器人模块组合装配而成,能够重构成不同的几何形态和结构,从而适应不同的作业任务要求。本论文主要对树状拓扑结构的模块化机器人的重构规划问题进行了研究,定义了构型重构的基本概念,提出了分支重构规划算法。这类模块化可重构机器人可以用树状拓扑结构图来描述。机器人的拓扑结构从自由树转化为有根树,然后分解为若干个分支结构,并按一定顺序排列,通过对各个分支结构的逐步比较和操作,完成重构过程。最后选定模块数目,进行了重构规划过程的仿真计算。结果表明,文中所述算法对于树状拓扑结构的模块化机器人的重构规划问题是有效的。     

机械手空间圆弧运动的一种有效轨迹规划方法

本文提出了机器人末端过空间三点作空间圆弧运动的 一种有效轨迹规划方法,并成功地应用于我们开发的电子装配机器人中．理论分析与实验分 析的结果一致．     

用Visual C++开发装配机器人微机屏幕示教盒

文章用VC＋＋6．0开发了一个精密装配机器人微机屏幕示教盒。该示教盒是基于PC机的精密装配机器人语言编程系统平台的组成部分。用户可通过鼠标操作该屏幕示教盒实现装配机器人的在线示教编程,从而可以替代传统的用单片机制作的示教盒。     

Faster RAM tackles data and marketplace bottlenecks

Random access memory (RAM) has long been considered a low-profile computing technology, lacking the impact of wireless networking and other hot areas of development. RAM's profile dropped even lower after the memory market fell into a severe slump several years ago and vendors started leaving the industry. However, as microprocessors have become much more powerful, RAM has become important again as a data bottleneck that is holding back PC and laptop performance gains. In response, vendors are developing more powerful RAM technologies. This has not only improved computer performance, it has also yielded considerable competition in the RAM marketplace and some important changes in the industry. As this has occurred, the cost per megabit of RAM has continued to fall. Thus, while the RAM market is still hurting because of low product prices, the technology is generating more interest     

RAM analysis of repairable industrial systems utilizing uncertain data

Industrial systems are mostly complex and considered as repairable. Also data, either collected or available (historical), reflecting their failure and repair patterns are limited, vague and imprecise due to various practical constraints. In such circumstances, their reliability, availability and maintainability (RAM) analysis may play an important role in any design modifications, if required, for achieving its optimum performance. However, it is difficult to estimate the RAM parameters of these systems up to a desired degree of accuracy by utilizing available information and uncertain data. This paper provides an idea, how can we estimate the RAM parameters of these systems by utilizing available information and uncertain data. For this purpose, Genetic Algorithms based Lambda–Tau (GABLT) technique is used. In this technique, expressions for the RAM parameters of the system are obtained by using traditional Lambda–Tau methodology and genetic algorithm is used to compute these parameters in the form of fuzzy membership functions utilizing quantified data in the form of triangular fuzzy numbers. A general RAM-Index is used for post RAM analysis to rank the subunits of the system on the basis of their performance. The approach has been applied to the press (series system) and washing (series–parallel system) units of a typical paper mill. The results may be helpful for the plant personnel for analyzing the systems’ behavior and to improve their performance by adopting suitable maintenance strategies.     

Microcomputer-based robot dynamic sensing using linear array sensor for object recognition and manipulation

This article presents a microcomputer-based robot dynamic sensing system by the use of the linear scanning approach for object recognition and manipulation. In this research, a 512 × 1 solid-state photodiode linear array sensor is used for dynamic scanning the object to be identified. An experimental prototype is built, which consists of a fully opened parallel jaw gripper and a 360d? turnable pedestal located between the jaws of the gripper. The sensor with the lens is mounted near the horizontal edge of one side of the gripper, and the illumination source is located directly on the other finger. The object to be identified is placed on the turnable pedestal. The simulated robot gripper can move vertically and the object will be scanned providing a two-dimensional image of the object. The object can be scanned in different views by adjusting the angle of the turnable pedestal. All the binary images which result are further analyzed for recognition and manipulation purposes. A Compaq microcomputer based on the Intel 8088 microprocessor is used as the host. A special interface between scanned video output, CPU, and video RAM memory is built and successfully tested.     

基于角色的群体感知模型实现机制

群体感知功能是计算机支持协同工作系统和群件系统必须支持的基本功能。文章分析了群体感知研究工作的现状,介绍了一种基于角色的群体感知模型RAM,给出了该模型实现的总体结构,并从角色任务树的组成和构造算法、角色管理框架和协议、感知模型引擎和系统调用API等几方面讨论了实现机制。最后给出了基于RAM的协同编著系统应用框架,讨论了在下一步研究中仍需解决的若干问题。     

A new content-defined chunking algorithm for data deduplication in cloud storage

Chunking is a process to split a file into smaller files called chunks. In some applications, such as remote data compression, data synchronization, and data deduplication, chunking is important because it determines the duplicate detection performance of the system. Content-defined chunking (CDC) is a method to split files into variable length chunks, where the cut points are defined by some internal features of the files. Unlike fixed-length chunks, variable-length chunks are more resistant to byte shifting. Thus, it increases the probability of finding duplicate chunks within a file and between files. However, CDC algorithms require additional computation to find the cut points which might be computationally expensive for some applications. In our previous work (Widodo et al., 2016), the hash-based CDC algorithm used in the system took more process time than other processes in the deduplication system. This paper proposes a high throughput hash-less chunking method called Rapid Asymmetric Maximum (RAM). Instead of using hashes, RAM uses bytes value to declare the cut points. The algorithm utilizes a fix-sized window and a variable-sized window to find a maximum-valued byte which is the cut point. The maximum-valued byte is included in the chunk and located at the boundary of the chunk. This configuration allows RAM to do fewer comparisons while retaining the CDC property. We compared RAM with existing hash-based and hash-less deduplication systems. The experimental results show that our proposed algorithm has higher throughput and bytes saved per second compared to other chunking algorithms.     

Optimizing web server RAM performance using birth–death process queuing system: scalable memory issue

Planning a powerful server imposes an enormous cost for providing ideal performance. Given that a server responding for web requests is more likely to consume RAM memory than other resources, it is desirable to provide an appropriate RAM capacity for optimal performance of server in congested situations. This can be done through RAM usage modeling and its performance evaluation. In the literature, modeling of RAM usage is not provided with mathematical modeling. We propose an approach to model RAM usage of such a server, based on birth–death process in this article. The model can be used to figure out an operation research problem of finding minimum RAM capacity covering intended constraints elicited from birth–death queuing system. We show how optimal RAM capacity can be obtained using our approach with an illustrative example.     

TP RAM的低功耗优化设计及应用

针对SoC中TP RAM的面积及功耗较大问题,提出一种优化设计方法。通过将SoC中的TP RAM替换成SP RAM,在SP RAM外围增加读写接口转换逻辑,使替换后的RAM实现原TP RAM的功能,保持对外接口不变。为了进一步降低功耗,使用自适应门控时钟,对地址总线进行格雷编码。将文中方法应用于一款多核SoC芯片,该芯片经TSMC 28 nm HPC工艺成功流片,die size为10.5 mm×11.3 mm,功耗为17.07 W。测试结果表明,优化后的RAM面积减少了25.2%,功耗降低了43.07%。     

含存储器数字电路系统的自动测试生成

已有的数字电路自动测试生成(ATPG)软件没有存储器的结构模型，不支持对存储器电路的自动测试生成。该文分析了2类存储器的功能特征，提出了面向测试的ROM和RAM结构模型的建立方法，其中，ROM根据所储存的数据等效成组合电路模型， RAM利用新建立的RAMBIT基元等效成利于测试的时序电路模型。将其应用于ATPG软件中，解决了含存储器数字电路的自动测试生成问题。     

基于稀疏RAM的逼近型N-TUPLE神经网络模型

将单层查找感知器 (SL L UP)中的 RAM式神经元替换为稀疏 RAM神经元 ,获得了一个基于稀疏 RAM的逼近型 N- tuple神经网络新模型 .新模型不仅可以缓和原 SL L UP的存储容量易于饱和的问题 ,而且使网络的表示更灵活、更广泛 ,更重要的是使得 N- tuple类型的网络直接处理大维数的样本、大样本集类的数据真正成为可能 ,而不需要二值化样本 .实验证实所提模型的合理性和有效性     

Exploration of trade-offs in the design of volatile STT–RAM cache

STT–RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT–RAM is inefficient in terms of energy and speed compared to SRAM and thus various device-/circuit-/architecture-level solutions have been proposed to tackle this inefficiency. One of the proposed solutions is redesigning STT–RAM cell for better write characteristics at the cost of shortened retention time (volatile STT–RAM). Because the retention failure of STT–RAM has a stochastic property, an extra overhead of periodic scrubbing with error correcting code (ECC) is required to tolerate the failure. The more frequent scrubbing and stronger ECC are used, the shorter retention time is allowed. With an analysis based on analytic STT–RAM model, we have conducted extensive experiments on various volatile STT–RAM cache design parameters including scrubbing period, ECC strength, and target failure rate. The experimental results show the impact of the parameter variations on last-level cache energy and performance and provide a guideline for designing a volatile STT–RAM with ECC and scrubbing.