Introducing the Intel i860 64-bit microprocessor

The authors describe the single-chip i860 CPU, a 64-bit, RISC (reduced-instruction-set-computer)-based microprocessor that executes parallel instructions using mainframe and supercomputer architectural concepts. They designed the 1,000,000-transistor, 10-mm×15-mm processor for balanced integer, floating-point, and graphics performance. They discuss the RISC core, memory management, floating-point unit, graphics, bus interface, software support, and interfacing to a DRAM system     

海量数据处理器MPC860T的DSP阵列设计

现代通信的数据量日益增加,数据处理的复杂度也日益加强,如何有效处理这些海量数据,是目前研究的难点,基于DSP阵列的数据处理系统是解决这些问题的有效方法。本文选用TI公司的TMS320C6713浮点型数字信号处理器以及Freescale公司的MPC860T通用通信处理器,设计了16颗浮点型DSP阵列来完成海量数据实时处理。详细介绍了该系统的DSP阵列的管理,包括复位、HPI数据管理通道设计。通过测试和实际应用验证,该系统不仅满足性能上的要求,还是一个通用的数据采集和处理平台。     

Jim Blinn's Corner-a trip down the graphics pipeline: subpixelicparticles

Reasons for subdividing pixels into subpixelic particles are discussed. Working with subpixel resolution in the floating-point domain is suggested as the easiest approach. To illustrate the use of floating-point pixel space, the arithmetic of two rendering algorithms is reviewed. The algorithms are an antialiased line renderer and a simple polygon tiler. Another use for subpixel resolution, i.e., doing antialiasing by subsampling is also considered. Using integer arithmetic in addition to subsampling is briefly discussed     

Least significant bit evaluation of arithmetic expressions in single-precision

Single-precision floatingpoint computations may yield an arbitrary false result due to cancellation and rounding errors. This is true even for very simple, structured arithmetic expressions such as Horner's scheme for polynomial evaluation. A simple procedure will be presented for fast calculation of the value of an arithmetic expression to least significant bit accuracy in single precision computation. For this purpose in addition to the floating-point arithmetic only a precise scalar product (cf. [2]) is required. If the initial floatingpoint approximation is not too bad, the computing time of the new algorithm is approximately the same as for usual floating-point computation. If not, the essential progress of the presented algorithm is that the inaccurate approximation is recognized and corrected. The algorithm achieves high accuracy, i.e. between the left and the right bound of the result there is at most one more floating-point number. A rigorous estimation of all rounding errors introduced by floating-point arithmetic is given for general triangular linear systems. The theorem is applied to the evaluation of arithmetic expressions.     

浮点到定点的高效翻译策略研究

动态二进制翻译中,在目标平台没有浮点部件、不支持浮点运算的情况下,浮点指令只能通过模拟解释执行。浮点指令的解释执行造成翻译系统效率急剧下降。通过将浮点指令运算转化为定点运算,解决了浮点指令在目标平台的翻译,为浮点指令的翻译找到了新的途径。在动态二进制翻译系统中进行实验,验证了翻译方法的可行性。实验显示翻译系统的性能有明显提升,含有浮点指令的比例越高,算法能够获得的加速比越高,对含有25%浮点指令的程序,该算法能达到1.55的加速比。     

在LonWorks网络中使用浮点数据

Neuron C是一种专门为Neuron芯片设计的程序设计语言。它在ANSIC的基础上进行了扩展，是开发LonWorks应用的有力工具。Neuron C不直接支持ANSIC中浮点数的算术和比较运算，但是它提供了一个浮点函数库，从而允许使用符合IEEE754标准的浮点数。文中详细介绍了Neuron C中浮点数据类型的定义、浮点常量的生成方法和浮点函数库的使用。通过一个实例LonWorks网络，演示了浮点数据的使用。     

Error detection of arithmetic expressions

Inspecting floating-point errors is essential to floating-point operations. In this paper, we present floating-point error detector (FPED), an inspector of floating-point errors for arithmetic expressions. FPED can pick a suitable benchmark generation approach by analyzing the distribution of the expression of a floating-point operation, thereby minimizing the possibilities of underreporting floating-point errors. FPED is also able to determine the significant sources of errors in a floating-point operation according to the frequencies of computation building blocks that contribute most to the floating-point errors, benefiting the follow-up optimizations of computation accuracies. We validate the correctness and functionalities of FPED by conducting experiments on the FPBench benchmark suite. The experimental results demonstrate that FPED can obtain more accurate detection results than the random detecting approach with respect to floating-point error detection. We also compare FPED with the existing dynamic error detection tools. The experimental results show that in most of the 33 test benchmarks, the maximum error results of FPED are greater than Herbgrind and the detection performance is higher than Herbgrind.

     

A pipelined interface for high floating-point performance with precise exceptions

Two options are presented that were considered for a pipelined interface between a central processing unit (CPU) and a floating-point coprocessor (FPU), along with the CPU recovery mechanisms that provide precise floating-point exceptions for each option. The first option supports parallel execution of both floating-point and integer instructions, while the second option pipelines only the execution of floating-point instructions. The use of the second option in National Semiconductor's 32532/32580 processor cluster because it offers high performance with significantly lower complexity. The 32532 microprocessor features a pipelined slave protocol that hides the CPU-FPU communication overhead for most floating-point instructions by pipelining their execution. A simple recovery mechanism implemented within the CPU maintains the precision of floating-point exceptions. As a result, the 32532 microprocessor supports very high floating point performance without sacrificing software compatibility with previous Series 32000 CPU-FPU clusters.<>     

并行浮点加法器架构与核心算法的研究

考虑到浮点运算在图形处理中的重要作用,依据速度和面积的优化原理,文章从两个方面对FAU结构中最复杂的双精度浮点加法进行了研究。其一:在结构上采用了三条相互并行的主线,设计了一种尽可能并行处理的三级浮点流水结构,极大地提高了运算的速度,节约了芯片资源;其二:对结构中制约浮点加法速度的关键运算——尾加和移位操作进行了创新设计与实现,并就设计的先进性和高速性与传统设计进行了参数比较和综合分析。     

基于编译时插桩的浮点异常检测方法

浮点数是实数的有限精度编码,在进行浮点计算时,可能会导致不精确或者异常的结果,因此实现有效的浮点异常检测方法很重要。现有异常检测方法不面向浮点数学函数,由此提出了一种面向浮点数学函数的异常检测方法。该方法依据IEEE-754标准中定义的上溢出、下溢出、被零除、无效操作和不精确5类异常,并结合申威高性能数学函数库中使用的浮点控制寄存器FPCR和IEEE-754标准定义的浮点异常产生条件的相关理论,通过将异常类型和浮点运算指令进行对应分类,在程序编译时进行插桩以检测出浮点数学函数中出现的异常,同时记录代码覆盖率。最后将该方法应用于数学函数库,对库中100多个浮点数学函数进行了测试实验。实验结果表明,该浮点异常检测方法能够有效检测各类异常。     

科学计算程序语言的浮点数机制研究

浮点数运算存在精度方面、比较方面以及舍入误差等方面的问题,而这些问题直接影响到科学计算的准确性、可靠性和安全性等等.目前有关浮点数的中文资料很少,很多教科书上在谈到浮点数时都是浅尝辄止,本文以C语言浮点数机制为研究基础,对浮点数的格式、精度与应用等方面问题进行了实证研究,获得了一些有用的结果.     

基于FPGA的浮点向量协处理器设计

为满足现代数字信号处理中大量数据的运算需求,利用ARM946和Xilinx公司的现场可编程门阵列芯片逻辑资源和IP库,设计专门用于浮点复数向量运算的64位协处理器,对相关浮点运算进行优化,并在硬件仿真平台上进行测试。结果表明,该协处理器可使浮点复数向量运算性能得到大幅提高。     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

基于改进4—2压缩结构的32位浮点乘法器设计

本文介绍一种用于高性能DSP的32位浮点乘法器设计,通过采用改进Booth编码的树状4-2压缩器结构,提高了速度,降低了功耗,该乘法器结构规则且适合于VLSI实现,单个周期内完成一次24位整数乘或者32位浮点乘。整个设计采用Verilog HDL语言结构级描述,用0.25um单元库进行逻辑综合.完成一次乘法运算时间为24.30ns.     

计算机浮点功能测试方法

浮点运算对衡量一台计算机的性能和可用性占着很大的比重，浮点功能测试是计算机功能测试的重要组成部分。在研究分析了IEEE754浮点标准相关内容和现有浮点测试包的基础上，提出了浮点测试技术的基本方法和策略。     

基于RISC-V浮点指令集FPU的研究与设计

针对目前浮点运算软件实现速度慢,不能满足嵌入式处理器实时性要求以及运算种类有限等问题,提出了一种基于RISC-V指令集的浮点处理器,能够执行加法、减法、乘法、除法、平方根、乘累加以及比较运算,完全符合IEEE 754-2008标准。在VCS仿真环境下对浮点处理器进行了功能验证,各模块均能满足正确性要求。将浮点处理器与一款开源处理器核蜂鸟E203集成,使用SMIC 0.18工艺库完成了逻辑综合,并在FPGA上对设计进行了测试。结果表明,该浮点处理器的逻辑门数仅为24 200,吞吐量为150 MFLOPS,与已公开文献的设计方案相比,硬件面积分别减少7%、1.5%。综合运行频率可达100 MHz。     

Optimale Basiswahl für eine Gleitkomma-Arithmetik

Choosing an internal floating-point representation for a binary computer with given word-length is influenced by two factors: the size of the range of admissible numbers and the precision of the respective floating-point arithmetic. In this paper “precision” is defined by a statistical model of rounding errors. According to this definition base 4 floating-point arithmetic on an average produces smaller rounding errors than all other floating-point arithmetics with a base 2^k, provided that the ranges of numbers have equal size.