智能复用EDA设计信息及调试文档自动生成技术

针对电子电路产品设计中调试文档编制存在的各种弊端,提出了一种智能复用EDA设计信息的调试文档自动生成技术。通过融合异构EDA设计数据,智能复用设计数据中的调试信息,利用多个调试文档库之间的关联性,自动、快速地生成各类调试文档。该技术实现的系统已经在电子电路设计中得到应用,结果表明,该技术不仅优化了调试流程,还提高了文档编制的自动性、快速性和规范性。     

基于EDA技术的PS/2接口电路设计

基于EDA技术,使用FPGA芯片和VHDL语言,设计了一种PS/2设备接口电路。介绍了硬件连接、通信协议、设计过程及仿真结果。采用自顶向下的设计思路,充分发挥EDA技术的优势,大大缩短了设计周期。软件仿真及硬件调试表明,设计中的各个模块之间能够正确地传送数据,性能稳定,达到了预期目标。     

设计旨在沟通：功能性产品设计中的三种语言

设计是人类移情作用的产物,旨在建立设计师与用户之间的双向沟通,达成双方的相互理解。然而,在功能性产品设计过程中,设计师的“命令”、产品的“应答”和用户的“请求”这三种语言之间存在着差别。文章旨在分析研究功能性产品设计过程中三种语言的交流过程,提出符合沟通逻辑的设计原则,对产品的用户需求满足起到一定的参考意义。     

基于Matlab的SCA调试分析组件开发与实现

在SCA波形组件上实现具体功能时需要大量的调试工作,通常的调试步骤是提取每个过程的输出数据进行分析,根据分析结果修改错误代码,然而该调试方式效率低下,数据提取过程复杂。为此,以Matlab引擎技术和curses图形库为基础,设计用于数据分析的Analysis Com波形组件。该组件按照SCA规范设计开发,在调试过程中避免了数据重复提取,并且在波形运行过程中能通过该组件直接调用Matlab进行数据分析。测试结果表明,Analysis Com波形组件可以在波形运行过程中快速准确地定位到数据发生错误的位置,完成对组件功能的验证,达到缩短组件开发周期的目的。     

Verilog HDL在现代EDA中的应用

本文通过一个简单的例子介绍了Verilog HDL语言的应用,对比地给出了功能仿真和时序仿真的波形,说明了实现电子电路的自动化设计（EDA）过程。     

EDA技术在竞争－冒险现象教学中的应用

在“数字电路”课程的教学中,引入EDA技术,利用EDA工具QuartusII中的原理图设计和时序波形仿真．在课堂上结合电教化教学手段,通过理论基础分析和电路波形仿真结果两个方面的内容,分析组合逻辑电路和时序逻辑电路工作状态转换过程中出现的竞争－冒险现象,探讨研究消除竞争－冒险现象的方法,并进行仿真验证。通过改进课堂教学方法,使学生深入理解数字电路中的竞争－冒险现象,提高教学效果。     

函数发生器的仿真设计与电路实现

以多波形函数发生器的设计为例,阐述理论分析、仿真设计和硬件实现相结合的电子电路设计方式。对函数发生器进行方案论证、单元电路设计,借助Multisim仿真软件建立仿真模型、进行仿真分析、优化设计方案,通过电路板制作、整体调试和性能指标测量完成硬件实现。实践表明,把虚拟仿真和硬件实现相结合,为提高电子电路设计质量和效率提供了一个有效手段,传统的设计方式与EDA技术的有机结合,将形成一种优越的创新性电子电路设计方式。     

高科技创想：让身体变得可以沟通

随着交互范围的扩大，我们从人与物之间的沟通，慢慢转向了通过物去建立人与人之间的沟通。在这个过程中，人的身体和大脑就成了本期专题里各种设计或构想的核心，同时也是设计师关注的主题。从那些不同寻常的创意中，人的身体和大脑以一种全新的方式被表达和阐释，它们变得可以沟通了。     

基于FPGA的A/D转换控制器设计

采用FPGA器件EP2C35F672C8对AD574进行实时采样控制,并将采集得到的数据暂存到SRAM中,以便进行分析和处理。整个设计过程采用EDA的设计流程,用硬件描述语言VHDL在QuartusII9.0中进行设计,给出了设计原理分析、硬件内部逻辑设计以及仿真波形输出,可用于模拟信号的高速实时采集。     

方家山核电工程仪控系统调试的典型问题分析

解决现场调试问题,首先要找到问题根源,理清设计、系统运行、试验方法等的上下游之间的关联,结合现场情况制定最佳解决方案。更好、更高效地解决现场出现的问题,来自于对现场情况的充分了解与调试备方的充分沟通,本文列举了一些系统调试出现的问题并详细论述了问题的解决过程。     

面向SoC设计的网格PSE资源管理器与原型实现

集成电路技术的发展始终存在着两个主要矛盾：集成电路工艺加工能力的快速增长与设计生产力的矛盾,集成电路复杂度增加与设计时间紧缩的矛盾。文章从网格技术的角度,把SoC设计过程中不同的设计资源,包括IP核、EDA设计工具软件、代码、设计专家信息等,通过统一的资源管理机制实现对各种设计资源的管理,解决SoC设计对资源共享和协同的需要,提高SoC设计的整体效率。同时介绍了面向SoC设计网格问题求解环境下资源管理器的原型实现。     

Implementation of the blit debugger

joff is an asynchronous, source-level, break-and-examine debugger for C programs running on the Blit, a programmable bitmap terminal, joff is implemented as two processes: a small process running in the terminal and a larger process running in a time-sharing host. The constraints on its design and a menu-driven user interface combine to present an unusual set of implementation difficulties. The way the problems were tackled and the degree to which they were solved may be interesting to those designing other debuggers. Operating system designers should assess the merits of a debugger that runs asynchronously with its subject and consider providing the necessary support.     

SoC芯片设计方法及标准化

随着集成电路技术的迅速发展，集成电路已进入系统级芯片（SoC)设计时代，SoC芯片的集成度越来越高，单芯片上的集成度和操作频率越来越高，投放市场的时间要求越来越短，为了实现这样的SoC芯片，设计越来越依赖IP模块的重用，SoC复杂性的提高和IP模块的多样化，SoC芯片中多个厂商不同IP模块的使用，导致了IP模块可重用的许多问题，IP模块和片上总线，以及EDA工具接口的标准化，是解决IP模块标准化的很好途径，另一方面，SoC芯片设计的复杂性和嵌入软件所占比重的增加，要求更高层次的系统抽象和软硬件的协同设计，使用更流地的设计进行系统的硬件设计和更有效的系统设计方法，描述了SoC芯片设计中的IP模块可重用技术以及所存在的问题，介绍了SoC IP模块和片上总线结构的标准化，讨论了基于C／C＋＋扩展类库的系统级描述语言和基于平台的SoC设计方法。     

基于WWW检索EDA资源信息的方法与技术

EDA（电子设计自动化）技术是当今电子技术发展的前沿之一,它将电子系统软件设计与硬件设计融为一体,为电子产品开发,电子系统设计,电子系统工程提供了全新的手段,阐述了在WWW上如何利用搜索引擎技术及工具进行EDA资源的搜集,整理工作,介绍了方法与技术可有效地提高EDA教学水平,具有很强的实践性。     

一种基于组的时序驱动布局规划方法

本文提出了一种基于组的时序驱动布局规划方法,它利用现有的EDA工具将网表划分为组,并充分利用设计师的体系结构经验进行布局、调整和优化。该方法能在设计早期获取较为准确的线负载模型,提高前端与后端的一致性,并且可以以组为单位规划电源和地的布局,提高布通率。该方法在已研制成功的32位嵌入式微处理器Estar的物理设计中得到实际应用。结果表明,该方法能够有效地改善关键路径时序和加快设计进程。     

Guest Editors' Introduction: GALS Design and Validation

Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have been proposing various GALS-based solutions. However, the tools, verification techniques, and testing methodologies for asynchronous designs are not as widespread as for synchronous digital design, leading to the hitherto limited usage of GALS design approaches. This special issue introduces some of the basic issues of GALS design and validation in the hardware domain. The hope is that this special issue will generate more interest by researchers and industry practitioners in creating design tools, techniques, and validation methodologies for GALS design.     

HFSS8．5在微带缝隙天线设计中的应用

介绍了微带缝隙天线中的维瓦尔迪天线,并借助于Ansoft公司的HFSS8.5软件进行了精确设计,通过将设计值与实验值进行比较,结果吻合。可以看出用EDA软件设计较之于传统的天线设计方法具有的优势,对于工程设计人员具有指导意义。     

Human factors of a microelectronic product: the central heating timer/programmer

The advent of microelectronics has enabled designers to incorporate considerably more functional capability and flexibility into products than was previously possible. Technical capabilities are no longer major constraints and designers are finding it increasingly difficult to choose between a vast range of alternatives. In an effort to narrow the range, designers are turning to behavioural scientists in marketing, ergonomics and psychology to guide them when selecting functions, specifying operating procedures and selecting components. This paper illustrates the application of human factors techniques to the analysis of problems with existing consumer products and to the synthesis of novel designs incorporating advanced microelectronics components. Within this general theme the paper concentrates on the design of a particular product - the central heating timer/programmer.     

Industrial Designers: Are You Ready for Foreign Markets? Assessing Designer Confidence and Prediction Accuracy in a Transnational Marketing Context

In order to boost sales in foreign markets and compete with emerging local competitors, global companies from developed countries are realizing that they need to develop products specifically for the local markets. Meanwhile, companies in developing nations are building up their design staff and seeking to establish their own global brands. This recent growth in design activity targeting overseas markets suggests the need for academic research to better understand the phenomenon of design expertise transfer across national borders. The present research explores industrial designers' expertise transfer across cultures with respect to knowledge calibration. Based on the literature on expertise and Shanteau's theory of expert competence, several hypotheses are developed regarding the main effect of culture, and the interaction between culture and expertise level, on design confidence and prediction accuracy. A three‐phase experimental study is conducted to test the hypotheses. Results suggest that both expert designers and non‐expert designers are poorly calibrated and overconfident. Nonetheless, expert designers are better calibrated when designing products for a foreign market than for their home market. Theoretical and managerial implications are discussed.     

Material light: exploring expressive materials

The control of material appearance has become richer than before, giving designers new expressive freedom. Designers need tools and techniques to handle this freedom when designing products. We present a simple but powerful technique to explore material expression in the conceptual phase of the design process. Colours and patterns are projected on foam and paper models to enable designers to quickly visualise and judge materials in context of the products shape. This paper is part of the 3AD design colloquium creative connections.