基于AMCC网络处理器的QoS技术

在分析QoS技术功能模块及AMCC网络处理器架构基础上,利用微码与高级语言混合编程模式设计并实现基于NP3450的网络设备数据平面软件,引入深度包分类、二次查表、三级调度及四组准入门限等机制,实现基于流的细颗粒度QoS管控。实验结果表明,该设计方案是可行的。     

NP带来防火墙变革

随着国内安全厂商越来越多地涌入网络安全高端市场,NP(Network Processor)技术变得越来越流行。国内许多防火墙公司纷纷投入力量开展相关研究,NP成为网络安全的热门话题。一、什么是NPNP是Network Processor的缩写,意为网络处理器。根据“国际网络处理器会议”的定义:网络处理器是一种可编程器件,它特定地应用于通信领域的各种任务,比如包处理、协议分析、路由查找、防火墙、QoS等。网络处理器器件内部通常由若干个微码处理器和若干硬件协处理器组成,且多个微码处理器在NP内部并行处理,通过预先编制的微码来控制处理流程。对于某些复…     

基于网络处理器IXP2400系统的软件设计

网络处理器高性能的包处理能力及可编程的灵活性适应了当前网络发展需求，广泛应用于高端路由器、边缘多业务宽带接入、媒体网关和安全等领域。基于网络处理器成功构建一个网络系统的关键在于网络处理器软件系统的设计与开发，其核心问题就是要软件系统充分发挥网络处理器灵活性和高性能的特点，面向网络处理器的硬件体系结构编程，合理利用网络处理器，为优化数据包处理的各种硬件资源设计高效的多处理器、多线程并行机制。本文以网络处理器IXP2400实现高速网络应用为例，介绍基于网络处理器系统的软件开发过程和设计方法，探讨开发高性能的微码软件的策略和技术。首先介绍了基于网络处理器系统的硬件体系结构配置和软件开发框架、应用软件的系统分析和总体设计，着重分析了基于网络处理器系统的多微引擎、多线程的并行处理机制，以及互斥问题和包排序问题的解决方法，最后讨论了系统的性能评估方法。     

基于NPA-X的POS接口板数据转发模块的实现

针对目前网络介质信息传输能力的迅猛增长和网络业务复杂多样化的形势,对基于NPA-X的POS接口板数据转发模块的实现及其性能进行了简要介绍。网络处理器NPA-X具有多引擎多线程结构,可进行高并行性处理,另外可通过微码进行编程,具有高灵活性,因此具有非常广泛的用途。本文首先介绍了网络处理器、NPA-X及其特点,其次介绍了POS接口板组成和基于NPA-X的数据转发模块,最后分析了此转发模块的性能。     

基于NPA-X的POS接口板数据转发模块的实现

针对目前网络介质信息传输能力的迅猛增长和网络业务复杂多样化的形势,对基于NPA-X的POS接口板数据转发模块的实现及其性能进行了简要介绍。网络处理器NPA-X具有多引擎多线程结构,可进行高并行性处理,另外可通过微码进行编程,具有高灵活性,因此具有非常广泛的用途。本文首先介绍了网络处理器、NPA-X及其特点,其次介绍了POS接口板组成和基于NPA-X的数据转发模块,最后分析了此转发模块的性能。     

基于NPA-X的POS接口板数据转发模块的实现

针对目前网络介质信息传输能力的迅猛增长和网络业务复杂多样化的形势,对基于NPA-X的POS接口板数据转发模块的实现及其性能进行了简要介绍。网络处理器NPA-X具有多引擎多线程结构,可进行高并行性处理,另外可通过微码进行编程,具有高灵活性,因此具有非常广泛的用途。本文首先介绍了网络处理器、NPA-X及其特点,其次介绍了POS接口板组成和基于NPA-X的数据转发模块,最后分析了此转发模块的性能。     

基于网络处理器的NAT协议实现技术

介绍了NAT的基本原理及其在网络边缘路由器中的应用，提出了基于网络处理器（Network Processor，简称NP）的NAT软件结构，并介绍了各个实现模块，对于基于NP的NAT实现技术的关键技术进行了讨论。     

浅析负载均衡的实现原理

随着当前信息技术与网络带宽的迅猛发展，千兆交换机、路由器的应用已随处可见。Intel研发的NP网络处理器用近似X86的价格实现了ASIC（专用集成电路）芯片的性能，它可以在两网口双向线速转发64字节的网络最短数据包。ASIC是用软件硬件化的方式来提高处理性能，所以它的NRE（不可逆投入）非常昂贵，并且其设计周期通常在1年以上。     

基于网络处理器IXP2350的IPSec协议实现设计

本文首先简单介绍了Intel IXP2350网络处理器的性能特点,以及采用此处理器作为IPSec协议的实现设计的原因;然后阐述了如何根据IXP2350硬件结构NPE1单元支持的加密/认证算法来实现IPSec协议,介绍了软件模块如何划分,并且详细说明了需要微码开发的软件处理流程,最终的实现说明了用此种分布式处理器实现IPSec比传统的集中式处理方式明显要优越。     

网络处理器中解决资源访问冲突的新方法

提出了采用硬件状态控制位寄存器和进程挂起模块相结合的设计思路,该方案不但成功避免了网络处理器微码转发程序多进程间资源访问冲突的问题,而且有效减少了微码转发程序中的指令个数,使传统软件方式下普遍存在的微码转发效率低的弊病得到彻底解决,提高了网络处理器的工作效率.     

Designing and supporting HMO,an integrated hardware microcode optimizer

This paper discusses an algorithm for optimizing the density and parallelism of microcoded routines in microprogrammable machines. Besides presenting the algorithm itself, this research also analyzes the algorithm's uses, design integration problems, architectural requirements and adaptability to conventional machine characteristics. Even though the paper proposes a hardware implementation of the algorithm, the algorithm is viewed as an integral part of the entire microcode generation and usage process, from initial high-level input into a software microcode compiler down to machine-level execution of the resultant microcode on the host machine. It is believed that, by removing much of the traditionally time-consuming and machine-dependent microcode optimization from the software portion of this process, the algorithm can improve the overall process.     

Vertical Migration for Performance Enhancement in Layered Hardware/Firmware/Software Systems

Vertical migration is a technique which improves system performance by moving software primitives through layers of application program and operating system software and microcode.     

Microcode Compression Using Structured-Constrained Clustering

Modern microprocessors have used microcode as a way to implement legacy (rarely used) instructions, add new ISA features and enable patches to an existing design. As more features are added to processors (e.g. protection and virtualization), area and power costs associated with the microcode memory increased significantly. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Moreover, with the adoption of multicore architectures, the impact of microcode memory size on the chip area has become relevant, forcing industry to revisit the microcode size problem. A solution to address this problem is to store the microcode in a compressed form and decompress it at runtime. This paper describes techniques for microcode compression that achieve significant area and power savings, while proposes a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50 to 62%. In addition, it proposes techniques that enable the reuse of (pre-validated) hardware building blocks that can considerably reduce the cost and design time of the microcode decompression engine in real-world designs.     

Automated Vertical Migration to Dynamic Microcode: An Overview and Example

We can achieve more optimal function assignments between microcode and software levels by applying techniques described herein to statically or dynamically microprogrammed processor design.     

数值协处理器微码电路的分析与检测

主要讨论用于完成数值协处理器各种运算的微码电路。简单介绍微码电路在协处理器中的重要性,具体介绍微程序控制模块的工作原理,微码电路的微码地址产生、微程序和微子程序的调用、四阈值微码的译码及微码电路的检测电路。     

Horizon: a retargetable compiler for horizontal microarchitectures

The vertical migration of complex application code into horizontal microcode makes traditional methods of handwritten and hand-optimized microcode with primitive assembly languages impractical. Higher-level languages that permit abstraction from low-level timing and concurrency details are considered a major step toward alleviating the problem. This approach is feasible only if compilers for these languages exist that can produce high-quality microcode and that can be targeted to new machines with modest effort and high reliability. An overview is provided of the Horizon retargetable microcode compiler, which facilitates the production of highly optimized microcode and the targeting of the compiler to specific machines     

Naming and binding in a vertical migration environment

Achieving maximum performance through migration of functions from software to microcode requires rethinking the linkage editing process. An object-oriented model of naming and binding clarifies the alternative abstractions available in naming and linking across the macro-micro machine boundary. Alternative abstractions for sharing micro-objects and for dynamic use of micro-objects are presented and their implementations discussed. The conclusions are based on actual implementations     

Javacard CPU的设计与实现

支持Javacard技术标准是智能卡的发展方向，目前的Javacard系统大多是采用软件虚拟机的方式来解释执行或者通过just-in-time方式执行Java指令，系统软件平台本身占用了大量的资源，且执行效率不高。解决这些问题的方法就是实现硬件Javacard指令处理器。该文给出了一种基于微码的Javacard指令处理器的FPGA设计和实现，以Javacard CPU为核心搭建Javacard CPU测试平台，并将其集成在一块FPGA上实现。