给定偏差约束下的时钟布线局部拓扑构造优化算法

提出一种时钟树布线算法,在给定偏差约束下,采用新的匹配策略考虑偏差约束进行局部拓扑优化,优先匹配延迟目标大的结点,将其置于时钟树拓扑结构底层;结合缓冲器的插入,抑制了蛇行线的产生．实验结果表明,对使用过时钟偏差调度算法优化后的电路,该算法可在时钟布线阶段有效地减少时钟线网中连线与缓冲器的总电容．     

Reliable buffered clock tree routing algorithm with process variation tolerance

1 Introduction The clock distribution network design is a very challenging task, because the per-formance and functionality of the whole synchronous system directly depend upon the clock signals. Clock skew is manifested by a lead/lag relationship between the clock signals. Conventional clock designs always demand a zero clock skew system, since they think that clock skew may limit the maximum operation frequency. Exact zero skew was first accomplished in ref. [1], and then DME (Deferred-Mer…     

VLSI中高性能X结构多层总体布线器

X结构带来物理设计诸多性能的提高,该结构的引入和多层工艺的普及,使得总体布线算法更复杂.为此,在XGRouter布线器的基础上,本文设计了三种有效的加强策略,包括:1)增加新类型的布线方式;2)粒子群优化(Particle swarm optimization,PSO)算法与基于新布线代价的迷宫布线的结合;3)初始阶段中预布线容量的缩减策略,继而引入了多层布线模型,简化了XGRouter的整数线性规划模型,最终构建了一种高性能的X结构多层总体布线器,称为ML-XGRouter.在标准测试电路的仿真实验结果表明,ML-XGRouter相对其他各类总体布线器,在多层总体布线中最重要的优化目标|溢出数和线长总代价两个指标上均取得最佳.     

高频时钟网络布线拓扑结构的曼哈顿平面切割线生成算法

在传统的Planar-DME拓扑划分算法的基础上,提出一种将欧几里德平面上的拓扑连接线转换成曼哈顿平面上的切割线并建立虚拟通道的算法,来进行连线调整,完成时钟网络的零时滞平面化布线．算法在开发软件原型Clockstar中得以应用。     

低功耗驱动的电路网表多级划分算法

在划分阶段因得不到实际线长值而无法精确计算功耗值.通过组合使用互连线的通路级数、通路级差和基本线长,提出一种新的独立线长预测方法.使用预测线长和开关活动性的乘积度量划分阶段的动态功耗,并将这一乘积作为权重赋给每条互连线;在聚类和细化处理阶段,尽量避免权重较大的互连线被分割,以实现低功耗驱动的多级划分.实验结果表明,该算法可有效地减小电路的功耗,并且对其他技术指标影响不大.     

基于模拟退火方法的多级时钟树的构建

在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。针对传统的时钟网络拓扑生成算法存在的不足，提出了时钟二叉树的“多级”模型并设计了基于模拟退火方法的时钟二叉树形成算法。用该算法对随机测试例子和标准标杆测试例子的测试中发现，较之传统的启发式算法，该算法能产生更好的测试结果。     

考虑布线资源松弛的X结构Steiner最小树算法

为了进一步考虑X结构,并充分利用障碍内可用布线资源,文中提出考虑布线资源松弛的X结构Steiner最小树算法.为了能够求解离散问题,在粒子的更新操作中引入交叉算子和变异算子.通过构建查找表,为整个算法流程提供快速的信息查询.提出角点选取策略,通过引入一些障碍角点,使粒子满足约束.最后构建精炼策略,进一步提高最终布线树的质量.实验表明,文中算法充分利用障碍内可用布线资源,有效缩短总布线长度,取得较佳的总布线长度.     

高性能众核处理器芯片时钟网络设计

随着芯片工艺演进与设计规模增加,高性能众核处理器芯片时钟网络设计面临时序和功耗的全方位挑战。为降低芯片时钟网络功耗并缓解时钟网络分布受片上偏差影响导致的时钟偏斜,在H-Tree+MESH混合时钟网络结构的基础上,结合新一代众核处理器芯片面积大及核心时钟网络分布广的特点,基于标准多源时钟树设计策略构建多源时钟树综合（MRCTS）结构,通过全局H-Tree时钟树保证芯片不同区域间时钟偏斜的稳定可控,利用局部时钟树综合进行关键路径的时序优化以实现时序收敛。实验结果表明,MRCTS能在保证时钟延时、时钟偏斜等性能参数可控的基础上,有效降低时钟网络的负载和功耗,大幅压缩综合子模块的布线资源,加速关键路径的时序收敛,并且在相同电源电压和时钟频率的实测条件下,可获得约22.15%的时钟网络功耗优化。     

面向裕量优化的高效时钟偏差规划和延迟提取

为了减少时钟偏差规划所需的时间,提出一种准线性时间复杂度的时钟偏差规划方法.该方法以整数来描述延迟大小的时钟偏差规划算法,限制每次对时钟延迟调整的步进至少为1,降低了算法的时间复杂度;改变了传统的预先生成完整的时序图作为算法输入的流程,采用一种新的增量式延迟提取策略为时钟偏差规划算法提取关键边的权重,减少了生成时序图所需要的时间.实验结果表明,采用文中方法进行时钟偏差规划的效率很高,对包含数千触发器的基准测试电路,其运行时间仅为数十秒.     

一种基于结群的零偏差时钟布线算法

介绍了一种基于结群的零偏差时钟布线算法，该算法采用新的单元匹配策略，递归地把时钟节点划分成2个负载和半径比较均衡的子集，结合缓冲器的适当插入，产生一棵零偏差的时钟布线树。实验表明，结群处理对处理规模较大的电路快速有效，时钟延迟得到了明显减少。     

Branch pipe routing based on 3D connection graph and concurrent ant colony optimization algorithm

Pipe routing, in particular branch pipes with multiple terminals, has an important influence on product performance and reliability. This paper develops a new rectilinear branch pipe routing approach for automatic generation of the optimal rectilinear branch pipe routes in constrained spaces. Firstly, this paper presents a new 3D connection graph, which is constructed by extending a new 2D connection graph. The new 2D connection graph is constructed according to five criteria in discrete Manhattan spaces. The 3D connection graph can model the 3D constrained layout space efficiently. The length of pipelines and the number of bends are modeled as the optimal design goal considering the number of branch points and three types of engineering constraints. Three types of engineering constraints are modeled by this 3D graph and potential value. Secondly, a new concurrent Max–Min Ant System optimization algorithm, which adopts concurrent search strategy and dynamic update mechanism, is used to solve Rectilinear Branch Pipe Routing optimization problem. This algorithm can improve the search efficiency in 3D constrained layout space. Numerical comparisons with other current approaches in literatures demonstrate the efficiency and effectiveness of the proposed approach. Finally, a case study of pipe routing for aero-engines is conducted to validate this approach.     

优化线长和拥挤度的增量式布局算法

随着IC技术的发展，降低连线拥挤度已经成为一个保证布线成功率的至关重要的因素．提出一种标准单元增量式布局算法C-ECOP．该算法通过一个新型的布线估计模型来精确估算布局以后的走线情况，利用力驱动的方法进行单元插入和单元推移来消除局部拥挤，同时进一步优化线长．来自美国工业界的测试实例表明，该算法能够很好地消除走线局部拥挤，同时尽量维持原有布局方案的电路性能，并且具有很高的效率．     

抗工艺变化的时钟偏差规划

提出了在时钟偏差规划过程中减小中心误差平方值的增量式松弛量分配方法.在给定的时钟周期下,根据当前约束条件中所包含的组合电路的最大/最小时延值的权重,合理地为具有不同变化量的约束条件边界分配不同的松弛量.实验结果表明:该方法可以有效地分配偏差值与约束边界间的安全区,从而大幅提高在工艺变化条件下电路的可靠性.     

高速IC设计技术

本文叙述了实现高速ＩＣ的设计技术，包括延时分析技术，高层次综合，逻辑综合延时优化技术，延时优化驱动布局与总体布线技术，控制时钟偏差技术以及各种技术的结合应用等。它覆盖了这一领域的前沿动态。     

Single clock partial scan

Existing partial-scan designs use a separate scan clock to simplify scan flip-flop selection and test generation methods. Such designs require multiple clock trees and create clock-signal routing problems that, in general, require tight control of clock skew. The author examines using the system clock for the scan operation and includes experimental results based on ISCAS89 benchmark circuits     

G-Tree:基于引力指向技术减少拐弯的Steiner树算法

提出一种基于引力指向技术、以减少拐弯数为目标的最小直角Steiner树构造算法G-Tree.利用一个节点受到其他节点的引力来决定它的移动方向,并采用引力加权以考虑减少拐弯数,生成Steiner树后对拐弯数进行了进一步优化.减少拐弯数有助于在布线阶段减少可能的通孔,从而增强电路的可靠性和可制造性.实验结果表明,G-Tree算法在减少布线树的拐弯数方面有明显的效果.     

Measurement and performance of a cognitive packet network

As the size of the Internet grows by orders of magnitude both in terms of users, number of IP addresses, and number of routers, and as the links we use (be they wired, optical or wireless) continuously evolve and provide varying reliability and quality of service, the IP based network architecture that we know so well will have to evolve and change. Both scalability and QoS have become key issues. We are currently conducting a research project that revisits the IP routing architecture issues and proposes new designs for routers. As part of this effort, this paper discusses a packet network architecture called a cognitive packet network (CPN), in which intelligent capabilities for routing and flow control are moved towards the packets, rather than being concentrated in the nodes. In this paper we outline the design of the CPN architecture, and discuss the quality-of-service based routing algorithm that we have designed and implemented. We then present our test-bed and report on extensive measurement experiments that we have conducted.     

无线传感器网络时钟参数追踪与一致性同步*

针对无线传感器网络分布式时钟同步问题,本文提出了基于卡尔曼滤波的最大一致性时钟同步算法。在获得硬件时钟参数后,通过设置预定偏斜目标,各节点可不通过网络交换来调整时钟偏斜。为了进一步使节点间时钟偏移达到同步,本文设计了最大一致性控制方案来补偿节点,并基于图论给出算法收敛性证明。仿真结果表明本文的算法能够快速跟踪硬件时钟参数,较加权最大一致性时钟同步算法收敛速度更快,全局平均同步误差下降了一个数量级。     

Equispreading tree in Manhattan distance

The equispreading tree on the plane with Manhattan distance, which is a Steiner tree such that all paths from the root to all leaves have the same length, is analyzed. This problem is not only fundamental in computational geometry but also critical for equidistant routings in VLSI clock design. Several characteristics for the trees are discussed together with an algorithm constructing equispreading trees in the bottom-up fashion. This algorithm achieves linear time and space complexity with respect to the number of leaves, and minimizes the path length from the root to leaves. Furthermore, this paper shows that the shortest-path-length equispreading trees are related to the smallest enclosing circles in Manhattan distance.     

Combining temporal partitioning and temporal placement techniques for communication cost improvement

In this paper, we present a typical temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the communication cost of the design. This aim can be reached by minimizing the transfer of data required between design partitions and the routing cost between FPGA modules. Consequently, our algorithm is composed by two main steps. The first step aims to find a temporal partitioning of the graph. This step gives the optimal solution in term of communication cost. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest routing cost between modules. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the communication cost compared with others famous approaches used in this field.