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1.
基于模块的运算部件模拟验证研究与实现   总被引:2,自引:1,他引:2  
周旭 《计算机工程》2003,29(6):21-23
提出一种基于模块的运算部件模拟验证方法,其基本思想是:针对运算部件模块,从通用的C测试程序中提取出模拟和仿真的输入向量;并对运行结果进行分析。利用该方法针对浮点乘法部件的验证过程说明,该方法可减少系统仿真时间,加速功能部件的逻辑验证,从而提高对处理器调试的速度。  相似文献   

2.
支持片上在线调试是嵌入式SoC设计目标之一;现有的片上调试系统多基于扫描链技术,SoC系统的功能设计和调试设计必须同步,这种紧耦合的设计方法移植性差、通用性弱,与SoC系统IP复用的理念不符;基于此,提出了一种基于片上标准总线的SoC在线调试方法,该方法引入调试主设备的概念,复用片上总线传输实时调试数据,实现了对SOC外围IP的在线调试,同时通过引入调试支持单元和调试处理模块实现了对处理器主设备的总线访问调试;该方法适用于以标准总线结构互联的SOC系统,具有适用性广、调试功能丰富、调试接口多样、调试效率高等优点;该方法在以SPARC处理器为处理核心、AMBA总线为互联的SoC系统中进行了实现和在线调试验证,实验表明满足SoC的调试需求。  相似文献   

3.
随着处理器架构的发展,高性能异构多核处理器不断涌现.由于高性能异构多核处理器的设计十分复杂,为了降低设计风险,缩短验证周期,提前进行软件开发,复现硅后问题等,通常需要搭建现场可编程门阵列(field programmable gate array,FPGA)的原型验证平台,并基于FPGA平台开展种类繁多,功能各异的软硬协同验证和调试工作,提出的基于同构FPGA平台对异构多核高性能处理器的FPGA调试、验证方法,有效地利用了异构多核处理器的架构特征,同构FPGA的对称特点,以层次化的方法自顶向下划分FPGA,自底向上构建FPGA平台.结合差速桥、自适应延迟调节、内嵌的虚拟逻辑分析仪(virtual logic analyzer,VLA)等技术可快速完成FPGA平台的点亮(bring-up)和部署.所提出的多核互补,核间替换模拟的调试SHELL等方法可以快速完整地对目标高性能异构多核处理器进行FPGA验证.通过该FPGA原型验证平台,成功地完成了硅前验证,软硬件协同开发和测试,硅后问题复现工作,并为下一代处理器架构设计提供了快速的硬件平台.  相似文献   

4.
介绍了一种基于DSP的小型八通道微弱信号被动声定位系统的软硬件设计与实现.采用低噪声放大技术进行模拟预处理,由两片级联的A/D芯片实现多通道同步采样,并运用高性能低功耗DSP作为主处理器,采用数字内插波束形成的方法进行仿真与编程,最后进行调试和实验.结果表明该系统能够对微弱信号进行准确定位.  相似文献   

5.
面向国产处理器核心性能提升的实际需求,针对处理器核RTL设计中可能出现的性能缺陷问题,提出了一种基于RT L仿真的轻量级处理器核性能分析框架.该性能分析框架基于定向和随机测试激励,通过对基准处理器核(Base Core)和新一代处理器核(New Core)的RT L设计进行快速模拟仿真,并对模拟结果进行对比分析,从而发现New Core在RTL设计过程中可能引入的性能缺陷.基于该性能分析框架,结合实际应用场景给出了测试方法和测试结果.实践表明,该性能分析框架能够快速对New Core的RT L设计的性能预期进行验证,从而发现New Core在RT L设计过程中可能引入的性能缺陷,有效加速新一代处理器核的研制进程.  相似文献   

6.
该文研究非线性混沌力学系统的图形化建模可视化仿真计算问题。通过建立统一的可视化仿真实验框架,实现了一具高度一体化的混沌系统图形建模和可视化仿真环境;与基于常规高级程序设计语言的混沌计算机模拟技术相比,该方法避免了传统意义上的混沌方程算法编程和调试过程,变可对混沌参数进行自动慑动分析及最优设计。  相似文献   

7.
为了提高星载嵌入式软件的可靠性和安全性,解决硬件测试环境构建困难、成本昂贵以及运行状态难以监控的局限性,提出了一种基于SPARC V8的星载嵌入式软件全数字仿真平台设计和实现方法。介绍了全数字仿真平台实现的关键技术,包括CPU指令集仿真、寄存器仿真、存储器仿真、中断控制器仿真、串口仿真、定时器仿真、虚拟外设模型仿真以及设备管理器和平台时序设计。全数字仿真平台与基于硬件的测试平台相比具有可重用性强、可快速搭建、成本低廉、高可控性、调试和测试手段丰富、支持故障注入等优点。该全数字仿真平台已在星载嵌入式软件型号研制中得到了应用,基于此平台可快速搭建虚拟目标机和虚拟外设环境,进行星载嵌入式软件运行仿真、调试验证等工作。  相似文献   

8.
DSP系统软件开发通常包括模拟阶段和仿真阶段.模拟在设计的最初阶段开始进行,不需要硬件支持,只需在计算机上运行软件模拟器,可实现代码的初步调试.仿真是将代码下载到目标板上调试、运行,一般需要利用JTAG.JTAG一端与DSP相连;另一端与主机相连,可实现代码下载、代码运行、变量查看、变量设置等.  相似文献   

9.
为保证基于FPGA数字心率计设计的性能,心率信号处理的模拟电路设计至关重要,由于外围电路存在噪声干扰,如何优化设计该电路,以有效地提取心率信号是传统设计的难点.利用Multisim仿真,可以很好地解决传统设计方法难以实现的电路优化设计.Multisim仿真把传统的硬件设计、调试、仿真集成在一个软件环境下,边设计边修改边调试,经过不断地参数设计和电路的调试,将心率模拟信号处理电路分为前级、中级和末级多级放大,低通、高通和陷波多级滤波,最终经过整形得到心率的数字信号.实践表明,改进电路有效地去除噪声,可提取正确心率信号,达到了理想的设计效果.证明仿真设计为信号处理电路提供了一个有效手段.  相似文献   

10.
旋转可变差动变压器(RVDT)信号仿真设备在航空计算机的设计、调试和RVDT数据采集系统的校准等方面起着举足轻重的作用;文中通过对RVDT传感器工作原理深入的剖析,提出基于PXIe总线的RVDT信号仿真方法;文章重点研究了RVDT传感器工作原理及输出特性,阐述了RVDT仿真设备的设计和实现,最后使用RVDT数采板卡CPCI-75C3对RVDT仿真设备进行了验证,结果表明该设备仿真精度高,响应速度快,运行稳定。  相似文献   

11.
12.
基于HLA的三维虚拟环境   总被引:6,自引:1,他引:6  
在分析了HLA体系结构及运行支撑框架(RTI)的基础上,提出了一个基于HLA的三维虚拟环境的设计和实现方案。阐明了此类系统的设计方法,着重分析了系统实现中涉及的仿真对象模型、信息交互机制、程序控制逻辑、坐标转换、实时性等关键技术问题和解决方案。最后在使用WindowsNT4.0的PIII高档微机平台上实现了该系统。实验表明,在综合分布交互系统SSS中,该分系统可实现与其它分系统的正确交互,场景刷新速率最高可达20帧/秒,基本满足实时性要求。  相似文献   

13.
RPM enables rapid prototyping of different multiprocessor architectures. It uses hardware emulation for reliable design verification and performance evaluation. The major objective of the RPM project is to develop a common, configurable hardware platform to accurately emulate different MIMD systems with up to eight execution processors. Because emulation is orders of magnitude faster than simulation, an emulator can run problems with large data sets more representative of the workloads for which the target machine is designed. Because an emulation is closer to the target implementation than an abstracted simulation, it can accomplish more reliable performance evaluation and design verification. Finally, an emulator is a real computer with its own I/O; the code running on the emulator is not instrumented. As a result, the emulator looks exactly like the target machine (to the programmer) and can run several different workloads, including code from production compilers, operating systems, databases, and software utilities  相似文献   

14.
Early estimation of application-specific power consumption has become one of the major constraints of modern ASIC design. While in early stages of the design process precise power consumption can only be obtained from very time consuming gate-level (GTL) simulation, power estimation methodologies aim to reduce computational overhead by deriving models to approximate power consumption on higher levels. This work presents an FPGA accelerated power estimation methodology for programmable processors based on a hybrid functional level (FLPA) and instruction level power analysis (ILPA) that can be mapped onto an FPGA together with the functional emulation. It enables fast and accurate estimation of application-specific power consumption and energy per task which is crucial for power-aware design of embedded processor architectures. The approach allows both hardware and software designers to optimize their implementations not only for processing performance but also for power efficiency. The power emulation methodology and considerations for the FPGA implementation of the power estimation is described in detail. Model validation against GTL power simulation and results are given for a typical embedded RISC processor and a commercial-grade Application Specific Instruction Set Processor (ASIP). Power consumption models yield fast and accurate power estimation with a %MAE of less than 9% and NRMSE of less than 7% enabling co-optimization of both hardware and software with respect to power consumption in early design stages.  相似文献   

15.
In order to achieve an optimum performance of a given application on a given computer platform, a program developer or compiler must be aware of computer architecture parameters, including those related to branch predictors. Although dynamic branch predictors are designed with the aim of automatically adapting to changes in branch behavior during program execution, code optimizations based on the information about predictor structure can greatly increase overall program performance. Yet, exact predictor implementations are seldom made public, even though processor manuals provide valuable optimization tips. This paper presents an experimental flow with a series of microbenchmarks that determine the organization and size of a branch predictor using on‐chip performance monitoring registers. Such knowledge can be used either for manual code optimization or for design of new, more architecture‐aware compilers. Three examples illustrate how insight into exact branch predictor organization can be directly applied to code optimization. The proposed experimental flow is illustrated with microbenchmarks tuned for Intel Pentium III and Pentium 4 processors, although they can easily be adapted for other architectures. The described approach can also be used during processor design for performance evaluation of various branch predictor organizations and for testing and validation during implementation. Copyright © 2004 John Wiley & Sons, Ltd.  相似文献   

16.
In this paper, we describe how our computational model can be used for the problems of processor allocation and task mapping. The intended applications for this model include the dynamic mapping problems of shrinking or spreading an existing mapping when the available pool of processors changes during execution of the problem. The concept of problem edge class and other features of our model are developed to realistically and efficiently support task partitioning and merging for static and dynamic mapping. The model dictates realistic changes in the computation and communication characteristics of a problem when the problem partitioning is modified dynamically. This model forms the basis of our algorithms for shrinking and spreading, and yields realistic results for a variety of problems mapped onto real systems. An emulation program running on a network of workstations under PVM is used to measure execution times for the mapping solutions found by the algorithms. The results indicate that the problem edge class is a crucial consideration for processor allocation and task mapping  相似文献   

17.
SMA:前瞻性多线程体系结构   总被引:4,自引:1,他引:3  
肖刚  周兴铭  徐明  邓鹍 《计算机学报》1999,22(6):582-590
提出了一种新的ILP处理器体系结构-前瞻性多线程体系的结构,简称SMA.它结合了前瞻性执行机制和多线程执行机制,以整个线程为长步进行前瞻性执行,多个线程并行执行并且共享处理器硬件资源,这样,处理器既通过组合每个线程的指令窗口形成一个大的动态指令窗口,开发出程序中更大的ILP,又利用多线程执行机制屏蔽各种长延迟操作,达到较高的资源利用率;介绍了SMA执行模型,并讨论了SMA处理器的实现和其中的关键技  相似文献   

18.
网络处理嚣是专门为网络处理而设计的处理嚣,其指令集是软硬件的界面,指令集的设计对性能有较大的影响.本文提出了一种针对高频率指令对-HFIP的组合优化方法,该方法充分利用了网络处理器基准程序里指令执行过程中的动态相关性,开发了simpIescalar模拟嚣的指令格式里未使用的空住作为新指令的扩展域.采用量化的方法对实验结果进行分析.模拟结果显示该方法合理有效,在提高网络处理器性能的同时有效降低指令cache的功耗.实现性能/功耗的权衡.  相似文献   

19.
This paper describes a language for studying the behaviour of programs, based upon the data collected while these programs are executed by a computer. Besides being a useful tool in debugging, the language is also valuable in the experimental evaluation of the complexity of algorithms, in studying the interdependence of conditionals in a program and in determining the feasibility of transporting programs from one machine to another. The program one wishes to analyse is written in an Algol 60-like language; when the program is executed it automatically stores, in a data base, the information needed to answer general questions about computational events which occurred during execution. This information consists (basically) of the list of labels passed while the program is being executed, and the current values of the variables. Since the list of labels is describable by regular expressions, these expressions can also be used to identify specific subparts of the list and therefore allow access to the values of the variables. This constitutes the basis for the design of the inquiry language. The user's questions are automatically answered by a processor which inspects the previously generated data base. The paper also presents examples of the use of the language and describes the implementation of its processor.  相似文献   

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