JSP数据库连接技术在构建信息网站中的研究

首先介绍了信息系统的用途和JSP技术的相关知识，然后讲述了JSP数据库接技术的两种方法，即JDBC（JavaBean）技术和连接池(Connection Pool)技术的基本原理和使用方法，并对它们的优缺点进行了分析比较，最后结合一个信息网站的实例讨论了这两种技术的使用方法，通过两种方法的结合使用，发挥了各自的优点，增加了浏览器的访问效率，提高了数据库的访问速度，充分发挥了数据库系统的工作性能，取得了很好的使用效果。     

计算机耐故障技术的探讨

本文以研究抗故障计算机为题，讨论了计算机系统的耐故障技术，叙述了耐故障技术的基础，从而引入了冗余性概念，同时还提出了耐故障技术的几种方法，并对几种方法进行了分析比较。     

网络安全信息关联与分析技术的研究进展

介绍了网络安全信息关联分析技术的背景，指出了该技术解决的问题。根据分析方法的不同，将该技术的现有方法分为4类：基于网络安全信息相似性的分析技术，基于攻击场景识别的分析技术，基于网络安全信息因果关系的分析技术，基于网络安全信息统计因果关系的分析技术。对每类方法的基本思想、现有技术以及存在的问题进行了阐述和分析，对未来的一些工作方向进行了展望。     

计算机网络拓扑发现技术研究

网络拓扑发现是通过收集网络传输的信息来研究网络连通结构的一项技术，在网络管理和网络安全评估发面具有重要意义。针对网络拓扑发现的关键问题，对网络拓扑发现的研究内容和研究目标进行了概括，分析了目前网络拓扑发现技术的国内外研究现状，从协议的角度归纳了目前几种网络拓扑发现技术的研究方法，阐述了每种方法的实现机理，同时指出了每种方法的使用范围和不足，最后讨论了网络拓扑发现技术的发展趋势。     

移动机器人路径规划技术的现状与发展

移动机器人技术是近年来的研究热点，路径规划技术是移动机器人技术研究中的一个重要领域。路径规划分为基于模型的环境已知的全局路径规划和基于传感器的环境未知的局部路径规划。该文详细地叙述了移动机器人路径规划技术的分类和发展现状，全局路径规划和局部路径规划中的各种方法，具体地分析了各种方法的算法过程，并指出了各种方法的优缺点，以及各种方法的改进的办法，最后对移动机器人路径规划技术的未来的发展趋势进行了展望。     

跨技术通信研究

随着物联网应用的广泛普及，同一区域尤其是室内环境中，各种各样无线网络协议共存的情况越来越普遍，从而导致信道竞争、信号冲突、吞吐下降等严重的干扰问题.相比于传统被动式的干扰避让、容忍和并发机制，不同无线技术之间主动进行数据共享和融合协调才是解决共存问题的关键.跨技术通信方法由此成为近年来学术界和工业界的研究热点，它能够实现异构设备之间直接的数据传输和信息交换.目前大部分的研究成果是针对具体的2种异构无线设备之间跨技术通信的使能技术，但缺少对跨技术通信方法的思考和总结.因此，在重新梳理相关研究的基础上，分析了跨技术通信方法产生的背景和研究意义，总结了现有工作提出的跨技术通信方法，包括基于数据包级别的跨技术通信方法和基于物理层级别的跨技术通信方法，并介绍了跨技术通信的相关应用场景.最后，展望了物联网技术的发展趋势，实现跨网络、跨频率、跨介质的互联互通.     

数据立方体聚集范围查询分块方法研究

范围查询是数据立方体数据分析的有效工具，预计算技术通过预先计算并存储范围查询的结果，可以实现快速的用户响应。近年来研究人员对基于MOLAP的预计算技术的研究主要以prefix sum及分块技术为基础。本文对预计算技术的分块方法进行研究，分析了现有分块技术的方法和性能，并提出了两种新的分块方法：嵌套分块和基于前缀区域边界的分块。本文对这两种分块的方法和特点做了阐述，研究表明这两种方法为分块技术提出了新的思路，是对现有分块方案的有力补充。     

基于物理的变形曲线曲面造型技术综述

现代工业技术的发展对CAD技术提出了越来越高的要求，传统的曲线曲面造型技术属于几何造型方法，已不能完全满足对现代工业产品尤其是柔性件的建模要求，基于物理的曲线曲面造型技术应运而生。该文首先介绍了基于物理的曲线曲面造型技术的产生和研究现状，主要分析了该技术方法的理论基础和实现原理，在此基础上讨论了该方法中求解控制方程的建立，重点比较了两种建模思想：Gossard静态模型和D—NURBS动态模型，并对不同控制方程的求解方法如差分法、有限元法和数学规划法也做了一定的综述。文章最后指出了这一造型技术的优势和存在的问题，探讨了今后发展的方向和思路。     

基于Internet的力反馈技术研究

论述了基于Internet的力反馈技术及其相关技术的发展和研究意义，综合机器人遥操作控制领域的理论方法，结合多媒体技术的最新发展，构建了一种基于事件的系统结构及其设计方法．基于该方法，分析了系统的可靠性、稳定性及力媒体传输的透明性，并设计了一个基于Internet的力反馈技术的系统实例．     

Web挖掘技术研究

随着互联网的飞速发展，Web挖掘技术已成为数据挖掘技术的一个研究热点。该文对Web挖掘的特点、方法进行了讨论，设计了一种快速有效的Web文档聚类方法，给出了实际测试结果，验证了Web挖掘技术的有效性。提出的Web挖掘技术有效地提高了该系统的协作能力。     

基于时序重构的时序调整软件HTC的设计与实现

高层次综合是近年来电子自动化（ＥＤＡ）领域中快速发展的一种技术，时序重构是高层次综合后端一种重要优化方法，文中介绍了基于地序重构时的时序调整软件ＨＴＣ的设计与实现，提出了时序调整软件ＨＴＣ中的主要优化算法，此算法与以前严格优化的计算时间复杂性较高的时序重构算法比较，是一种计算时间复杂性为线性的近似优化算法，最后给出了时序调整软件ＨＴＣ的电路实测测试结果，并与商用Ｓｙｎｏｐｓｙｓ公司的ＢＲＴ（ｂｅｈ     

Scheduling data-flow graphs via retiming and unfolding

Loop scheduling is an important problem in parallel processing. The retiming technique reorganizes an iteration; the unfolding technique schedules several iterations together. We combine these two techniques to obtain a static schedule with a reduced average computation time per iteration. We first prove that the order of retiming and unfolding is immaterial for scheduling a data-flow graph (DFG). From this nice property, we present a polynomial-time algorithm on the original DFG, before unfolding, to find the minimum-rate static schedule for a given unfolding factor. For the case of a unit-time DFG, efficient checking and retiming algorithms are presented     

用于高速逻辑电路优化的改进Retiming算法

时序重排是一种同步时序电路性能优化的重要方法,文中提出了一种改进时序重排算法,使时序重排可以更有效地与其经组合优化算法结合起来,共同提高同步时序电路的速度,在各种不同的测试电路上得到的实验结果显示,这种算法在与其它组合优化方法的结合上,较以往的时序重排算法有很大的改进。     

Understanding retiming through maximum average-delay cycles

A synchronous circuit built of functional elements and registers is a simple implementation of the semisystolic model of computation that can be used to design parallel algorithms. Retiming is a well-known technique that transforms a given circuit into a faster circuit by relocating its registers. We give tight bounds on the minimum clock period that can be achieved by retiming a synchronous circuit. These bounds are expressed in terms of the maximum delay-to-register ratio of the cycles in the circuit graph and the maximum propagation delayd _max of the circuit components. Our bounds do not depend on the size of the circuit, and they are of theoretical as well as practical interest. They characterize exactly the minimum clock period that can be achieved by retiming a unit-delay circuit, and they lead to more efficient algorithms for several important problems related to retiming. Specifically, we give anO(V ^1/2 E IgV) algorithm for minimum clock-period retiming of unit-delay circuitry. For non-unit-delay circuitry, we describe anO(VE Igd _max ) algorithm for minimum clock-period retiming. We also describe anO(V ^1/2 E lg²(Vd _max ) algorithm for retiming with clock period that does not exceed the minimum by more thand _max — 1. Finally, we give anO(E Igd _max ) algorithm for minimum clock-period pipelining of combinational circuitry.This research was supported in part by the Defense Advanced Research Projects Agency under Contract N00014-87-K-0825.     

Achieving full parallelism using multidimensional retiming

Most scientific and digital signal processing (DSP) applications are recursive or iterative. Transformation techniques are usually applied to get optimal execution rates in parallel and/or pipeline systems. The retiming technique is a common and valuable transformation tool in one-dimensional problems, when loops are represented by data flow graphs (DFGs). In this paper, uniform nested loops are modeled as multidimensional data flow graphs (MDFGs). Full parallelism of the loop body, i.e., all nodes in the MDFG executed in parallel, substantially decreases the overall computation time. It is well known that, for one-dimensional DFGs, retiming can not always achieve full parallelism. Other existing optimization techniques for nested loops also can not always achieve full parallelism. This paper shows an important and counter-intuitive result, which proves that we can always obtain full-parallelism for MDFGs with more than one dimension. This result is obtained by transforming the MDFG into a new structure. The restructuring process is based on a multidimensional retiming technique. The theory and two algorithms to obtain full parallelism are presented in this paper. Examples of optimization of nested loops and digital signal processing designs are shown to demonstrate the effectiveness of the algorithms     

Systolic Array Synthesis using SFG Representations

One of the important design problems in systolic array processing is the development of a systematic methodology for transforming an algorithm represented in some high level constructs into a systolic architecture specified by the timing of data movement and the interconnection of processing elements such that the design requirements are satisfied. In this paper a method using the SFG (signal flow graph) of a given algorithm to design systolic arrays through graphic mapping and retiming is presented. An algorithm is first represented by a DG (dependence graph). Then the DG is mapped into an SFG by a graph projection. Cut-set retiming procedures are then applied to derive a regular localised SFG from which a systolic array design can be obtained for the given matrix examples i.e. LU and QR decompositions.     

Using fixed-point semantics to prove retiming lemmas

Algorithms designed for VLSI implementation are commonly described by directed graphs, in which the nodes represent functional units and the arcs indicate communication links. We give a denotational semantics for such a graph in terms of the least fixed point of a set of (mutually recursive) function definitions, describing the outputs produced at each node as a function of time. This semantics is consistent with the conventional clocked operational semantics of the system. A retiming is a systematic modification of the internode delays of a design, often used to convert an algorithm design into a systolic form. The utility of such retimings in optimizing the behavior of designs is well known. We use fixed-point semantics to provide simple proofs of the correctness of certain retiming transformations from the literature and to justify other design transformations such as pipelining.     

Circuit retiming applied to decomposed software pipelining

This paper elaborates on a new view on software pipelining, called decomposed software pipelining. The approach is to decouple the problem into resource constraints and dependence constraints. Resource constraints management amounts to scheduling an acyclic graph subject to resource constraints for which an efficiency bound is known, resulting in a bound for loop scheduling. The acyclic graph is obtained by cutting some particular edges of the (cyclic) dependence graph. In this paper, we cut edges in a different way, using circuit retiming algorithms, so as to minimize both the longest dependence path in the acyclic graph, and the number of edges in the acyclic graph. With this technique, we improve the efficiency bound given for Gasperoni and Schwlegelshohn algorithm, and we reduce the constraints that remain for the acyclic problem. We believe this framework to be of interest because it brings a new insight into the software problem by establishing its deep link with the circuit retiming problem     

一种基于路径分类的时序重构算法

讨论了FEAS算法的实现问题，对FEAS算法进行了改进，并提出一种能快速的完成同步时序电路的时序重构变换的方法。通过基于ISCAS89标准测试电路的试验数据，说明了这种算法能快速的完成同步时序电路的时序重构变换。     

High throughput and energy efficient linear phase FIR filter architectures

High throughput, low complex and energy efficient linear phase FIR filter structures with low latency are highly desirable for most of the portable signal processing applications. Improving the throughput and energy efficiency while ensuring low latency and complexity is a difficult problem due to the trade-off between performance metrics. To this end, the design of linear phase filter based on the application of retiming and pipelining is proposed. The CPD, PDP, ADP and ELT of the proposed 16-tap linear phase FIR filter is reduced by 64.83%, 80.1%, 61.58%, and 62.49% respectively in comparison with FIR filter using flexible retiming and by 18.29%, 30.99%, 16.56%, and 12.82% respectively in comparison with the recent retiming based high throughput FIR filter. The 16-tap ECG denoising filter developed from the proposed filter structure provides excellent performances in terms of CPD, PDP, ADP and ELT as the algorithmic transformations are applied to an exact multiplier-less linear phase filter structure. It filters out PLI of 50 Hz, its harmonics and high frequency noises while providing improved denoising performances. The CPD, PDP, ADP and ELT of the proposed multiplier-less ECG denoising filter is reduced by 82.44%, 97.55%, 93.51%, and 81.27% respectively in comparison with a typical 17-tap FIR notch filter and by 70.06%, 99.82%, 99.68%, and 98.12% respectively in comparison with a typical Bartlett window based 256-tap FIR notch filter. Structural model VHDL coding is used for developing filters. For synthesis, Cadence software with gpdk 45 nm standard cell library is used and for simulation modelsim is used.