Data-Flow Frameworks for Worst-Case Execution Time Analysis

The purpose of this paper is to introduce frameworks based on data-flow equations which estimate the worst-case execution time (WCET) of real-time programs. These frameworks allow several different WCET analysis techniques with various precisions, which range from naïve approaches to exact analysis, provided exact knowledge on the program behavior is available. In addition, data-flow frameworks can also be used for symbolic analysis based on information derived automatically from the source code of the program.     

Timing Analysis for Instruction Caches

This paper contributes a comprehensive study of a framework to bound worst-case instruction cache performance for caches with arbitrary levels of associativity. The framework is formally introduced, operationally described and its correctness is shown. Results of incorporating instruction cache predictions within pipeline simulation show that timing predictions for set-associative caches remain just as tight as predictions for direct-mapped caches. The low cache simulation overhead allows interactive use of the analysis tool and scales well with increasing associativity.The approach taken is based on a data-flow specification of the problem and provides another step toward worst-case execution time prediction of contemporary architectures and its use in schedulability analysis for hard real-time systems.     

An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution

Previously published methods for estimation of the worst-case execution time on high-performance processors with complex pipelines and multi-level memory hierarchies result in overestimations owing to insufficient path and/or timing analysis. This does not only give rise to poor utilization of processing resources but also reduces the schedulability in real-time systems. This paper presents a method that integrates path and timing analysis to accurately predict the worst-case execution time for real-time programs on high-performance processors. The unique feature of the method is that it extends cycle-level architectural simulation techniques to enable symbolic execution with unknown input data values; it uses alternative instruction semantics to handle unknown operands. We show that the method can exclude many infeasible (or non-executable) program paths and can calculate path information, such as bounds on number of loop iterations, without the need for manual annotations of programs. Moreover, the method is shown to accurately analyze timing properties of complex features in high-performance processors using multiple-issue pipelines and instruction and data caches. The combined path and timing analysis capability is shown to derive exact estimates of the worst-case execution time for six out of seven programs in our benchmark suite.     

Supporting Timing Analysis by Automatic Bounding of Loop Iterations

Static timing analyzers, which are used to analyze real-time systems, need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. This paper describes three complementary methods to support timing analysis by bounding the number of loop iterations. First, an algorithm is presented that determines the minimum and maximum number of iterations of loops with multiple exits. Even when the number of iterations cannot be exactly determined, it is desirable to know the lower and upper iteration bounds. Second, when the number of iterations is dependent on unknown values of variables, the user is asked to provide bounds for these variables. These bounds are used to determine the minimum and maximum number of iterations. Specifying the values of variables is less error prone than specifying the number of loop iterations directly. Finally, a method is given to tightly predict the execution time of inner loops whose number of iterations is dependent on counter variables of outer level loops. This is accomplished by formulating the total number of iterations of a loop in terms of summations and solving the resulting equation. These three methods have been successfully integrated in an existing timing analyzer that predicts the performance for optimized code on a machine that exploits caching and pipelining. The result is tighter timing analysis predictions and less work for the user.     

Stochastic Prediction of Execution Time for Dynamic Bulk Synchronous Computations

We consider the problem of execution time prediction for non-deterministic multi-phase bulk synchronous computations in multiprocessors. We characterize the computations in two stochastic workload evolution models: additive and multiplicative. The additive model reflects the commutations in which the workload changes between phases are independent of processes' present workload. The multiplicative model becomes relevant when the workload change in a process is proportional to its load base. We take advantage of their salient features and show that conventional approaches based on central limit theorem in statistics are viable to predict the execution time for long run computations. By an elegant coordination of results from order statistics and convergence rates in the central limit theorem, we derive tighter bounds on execution time of short run computations, under some mild assumptions on their workload change distributions. Accuracy of the predictions is analyzed rigorously and verified by simulations.     

Analysis of Worst Case DMA Response Time in a Fixed-Priority Bus Arbitration Protocol

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage patterns of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. Finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within 20% for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.     

开源处理器Rocket的分支预测机制与性能评估

Rocket是基于RISC-V指令集架构的开源处理器,具有分支预测功能,其实现了GShare分支预测机制,在分析Rocket处理器分支预测处理过程、分支预测实现原理的基础上,利用模拟器进行了性能测试,并依据测试结果,对Rocket处理器分支预测参数配置给出建议.     

Real-Time Performance of Sorting Algorithms

In hard real-time systems tasks must meet their deadlines under guarantee. Soft real-time tasks may miss deadlines occasionally, as long as the entire system can provide the specified quality of service.In this paper we investigate the hard and soft real-time performance of sorting algorithms and compare it to their average performance. We show in which way the adequacy of an algorithm depends on the demanded performance criterium (hard, soft, or non real-time). The results provide a guideline to select the right sorting algorithm for a given application.     

Response Time Analysis of Asynchronous Real-Time Systems

In asynchronous real-time systems the time when all events occur can not be predicted beforehand. Systems with sporadic tasks, or that operate a protocol for sharing resources like the priority ceiling protocol, for example, are asynchronous real-time systems. In this paper, we present a sufficient and efficient response time based analysis technique for computing R _i(k), the worst case response time at each invocation k of the periodic tasks of real-time asynchronous systems. In addition, efficient idle time computation for asynchronous systems is presented. This analysis technique can be applied to the analysis of several process models including weakly hard real-time systems, and slack management techniques like aperiodic servers and slack stealing algorithms. It is also shown that the pattern of response times of tasks in a hyperperiod is pseudoperiodic and that the maximum response time instants tend to occur evenly separated within the hyperperiod.     

Symbolic Cache Analysis for Real-Time Systems

Caches impose a major problem for predicting execution times of real-time systems since the cache behavior depends on the history of previous memory references. Too pessimistic assumptions on cache hits can obtain worst-case execution time estimates that are prohibitive for real-time systems. This paper presents a novel approach for deriving a highly accurate analytical cache hit function for C-programs at compile-time based on the assumption that no external cache interference (e.g. process dispatching or DMA activity) occurs. First, a symbolic tracefile of an instrumented C-program is generated based on symbolic evaluation, which is a static technique to determine the dynamic behavior of programs. All memory references of a program are described by symbolic expressions and recurrences and stored in chronological order in the symbolic tracefile. Second, a cache hit function for several cache architectures is computed based on a cache evaluation technique. Our approach goes beyond previous work by precisely modelling program control flow and program unknowns, modelling large classes of cache architectures, and providing very accurate cache hit predictions. Examples for the SPARC architecture are used to illustrate the accuracy and effectiveness of our symbolic cache prediction.