Recognizing yield patterns through hybrid applications of machine learning techniques

Yield management in semiconductor manufacturing companies requires accurate yield prediction and continual control. However, because many factors are complexly involved in the production of semiconductors, manufacturers or engineers have a hard time managing the yield precisely. Intelligent tools need to analyze the multiple process variables concerned and to predict the production yield effectively. This paper devises a hybrid method of incorporating machine learning techniques together to detect high and low yields in semiconductor manufacturing. The hybrid method has strong applicative advantages in manufacturing situations, where the control of a variety of process variables is interrelated. In real applications, the hybrid method provides a more accurate yield prediction than other methods that have been used. With this method, the company can achieve a higher yield rate by preventing low-yield lots in advance.     

An online collaborative semiconductor yield forecasting system

Yield forecasting is a very important task to a semiconductor manufacturing factory which is a typical group-decision-making environment. Namely, many experts will gather to predict the yields of products collaboratively. To enhance both the precision and accuracy of collaborative semiconductor yield forecasting, an online expert system is constructed in this study. The collaborative semiconductor yield forecasting system adopts the client–server architecture, and therefore the necessity for all experts to gather at the same place is relaxed, which is especially meaningful for a multiple-factory case. To demonstrate the applicability of the collaborative semiconductor yield forecasting system, an experimental system has been constructed and applied to two random-access-memory products in a real semiconductor manufacturing factory. Both the precision and accuracy of forecasting the yields of the two products were significantly improved. Besides, the collaborative semiconductor yield forecasting system was also considered as a convenient platform for the product engineers or quality control staff from different factories to share their opinions about the yield improvement process of a product being manufacturing with the same technology in multiple factories.     

Defective wafer detection using a denoising autoencoder for semiconductor manufacturing processes

Defective wafer detection is essential to avoid loss of yield due to process abnormalities in semiconductor manufacturing. For most complex processes in semiconductor manufacturing, various sensors are installed on equipment to capture process information and equipment conditions, including pressure, gas flow, temperature, and power. Because defective wafers are rare in current practice, supervised learning methods usually perform poorly as there are not enough defective wafers for fault detection (FD). The existing methods of anomaly detection often rely on linear excursion detection, such as principal component analysis (PCA), k-nearest neighbor (kNN) classifier, or manual inspection of equipment sensor data. However, conventional methods of observing equipment sensor readings directly often cannot identify the critical features or statistics for detection of defective wafers. To bridge the gap between research-based knowledge and semiconductor practice, this paper proposes an anomaly detection method that uses a denoise autoencoder (DAE) to learn a main representation of normal wafers from equipment sensor readings and serve as the one-class classification model. Typically, the maximum reconstruction error (MaxRE) is used as a threshold to differentiate between normal and defective wafers. However, the threshold by MaxRE usually yields a high false positive rate of normal wafers due to the outliers in an imbalanced data set. To resolve this difficulty, the Hampel identifier, a robust method of outlier detection, is adopted to determine a new threshold for detecting defective wafers, called MaxRE without outlier (MaxREwoo). The proposed method is illustrated using an empirical study based on the real data of a wafer fabrication. Based on the experimental results, the proposed DAE shows great promise as a viable solution for on-line FD in semiconductor manufacturing.     

Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below

The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industry-wide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industry's growth. Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL - an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.     

An empirical study of design-of-experiment data mining for yield-loss diagnosis for semiconductor manufacturing

To maintain competitive advantages, semiconductor industry has strived for continuous technology migrations and quick response to yield excursion. As wafer fabrication has been increasingly complicated in nano technologies, many factors including recipe, process, tool, and chamber with the multicollinearity affect the yield that are hard to detect and interpret. Although design of experiment (DOE) is a cost effective approach to consider multiple factors simultaneously, it is difficult to follow the design to conduct experiments in real settings. Alternatively, data mining has been widely applied to extract potential useful patterns for manufacturing intelligence. However, because hundreds of factors must be considered simultaneously to accurately characterize the yield performance of newly released technology and tools for diagnosis, data mining requires tremendous time for analysis and often generates too many patterns that are hard to be interpreted by domain experts. To address the needs in real settings, this study aims to develop a retrospective DOE data mining that matches potential designs with a huge amount of data automatically collected in semiconductor manufacturing to enable effective and meaningful knowledge extraction from the data. DOE can detect high-order interactions and show how interconnected factors respond to a wide range of values. To validate the proposed approach, an empirical study was conducted in a semiconductor manufacturing company in Taiwan and the results demonstrated its practical viability.     

Combining negative binomial and Weibull distributions for yield and reliability prediction

A key productivity metric in semiconductor manufacturing is wafer test yield - the fraction of dies deemed functional following wafer probe testing. Wafer test yield is directly related to semiconductor manufacturing profitability: The higher the yield, the lower the cost of producing a functional chip, and therefore the greater the potential profit. Because wafer test yield is such a critical variable in a products profit potential, accurate yield projection models are essential to semiconductor manufacturers economic success. It is important to understand the correlation between defects causing yield loss and defects causing reliability failures. This article presents a modeling methodology and supporting data, demonstrating that yield and reliability defects can be directly linked in a unified model.     

The implementation of neural network for semiconductor PECVD process

In semiconductor manufacturing, the monitoring system has been developed very excellently and can be used for comprehensively collecting the historical data of process information and quality characteristics of equipment. However, due to the high turnover rate of personnel and the great variance in manufacturing process, the previous control technique by using intuition and experience of engineers for manufacturing process parameter settings to achieve good product quality is no longer appropriate. Therefore, this research establishes a quality predictor for analyzing the relationship between manufacturing process parameter setting and final product quality in the plasma-enhanced chemical vapor deposition (PECVD) of semiconductor manufacturing by applying the back-propagation neural network (BPNN) algorithm and Taguchi method. The experimental data are categorized into 500 pieces of training data and 150 pieces of verifying data. The proposed analysis method for using in the PECVD process of semiconductor manufacturing is verified by comparing the predicted film thickness of SiO₂ and the predicted refractive index of silicon dioxide films with the measured data. According to the comparison result, the proposed model has an excellent prediction capability of final product quality and can be applied in process control for related manufacturing fields.     

Economic Efficiency Analysis of Wafer Fabrication

Economic efficiency analysis of semiconductor fabrication facilities (fabs) involves tradeoffs among cost, yield, and cycle time. Due to the disparate units involved, direct evaluation and comparison is difficult. This article employs data envelopment analysis (DEA) to determine relative efficiencies among fabs over time on the basis of empirical data, whereby cycle time performance is transformed into monetary value according to an estimated price decline rate. Two alternative DEA models are formulated to evaluate the influence of cycle time and other performance attributes. The results show that cycle time and yield follow increasing returns to scale, just as do cost and resource utilization. Statistical analyses are performed to investigate the DEA results, leading to specific improvement directions and opportunities for relatively inefficient fabs. Note to Practitioners-Speed of manufacturing is an important metric of factory performance, yet it has long been a challenge to integrate its value into overall performance evaluation. However, for many semiconductor products, a predictable rate of decline in selling prices makes it possible to transform time value into monetary value. This study employs a novel method to incorporate a speed metric into economic efficiency evaluation and thereby provide a guideline for improving fab efficiency in manufacturing practice. Furthermore, this study integrates factory productivity and cycle time into a relative efficiency analysis model that jointly evaluates the impact of these two factors in manufacturing performance. In particular, we validate this approach with data from ten leading wafer fabs obtained by the Competitive Semiconductor Manufacturing Program and we discuss managerial implications.     

Discovering useful and understandable patterns in manufacturing data

Accurate planning of produced quantities is a challenging task in semiconductor industry where the percentage of good parts (measured by yield) is affected by multiple factors. However, conventional data mining methods that are designed and tuned on “well-behaved” data tend to produce a large number of complex and hardly useful patterns when applied to manufacturing databases. This paper presents a novel, perception-based method, called Automated Perceptions Network (APN), for automated construction of compact and interpretable models from highly noisy data sets. We evaluate the method on yield data of two semiconductor products and describe possible directions for the future use of automated perceptions in data mining and knowledge discovery.     

OEE improvement by pogo pin defect detection in wafer probing process

Microsystem Technologies - It is usually very difficult to find the causes of low yield performance in semiconductor manufacturing. In a typical wafer probing process, when the yield is low,...