High performance FPGA-based image correlation

Image correlation is widely used for image and picture processing. Typical applications of image correlation are object location, image registration and sub-image similarity measurement. However, image correlation requires the comparison of a large number of sub-images implying a large computational effort that may prevent its use for real-time applications. On the other hand, correlation computation is very well suited for FPGA implementations. In this work we present efficient architectures for the implementation of Zero-Mean Normalized Cross-Correlation using FPGAs with application to image correlation. In particular, we compare the implementations of correlation in the spatial and spectral domains. Experimental results demonstrate that FPGAs improve performance by at least two orders of magnitude with respect to software implementations on a modern personal computer. This speed-up makes the performance of correlation computation suitable for real-time image processing. The proposed architectures have been applied to a correlation-based fingerprint-matching algorithm, demonstrating that real-time processing requirements can be well satisfied with an FPGA-based implementation.     

Open generification

To what extent can software ‘travel’ to organizations and countries for which it was not designed for, and how important are local contexts for a successful design and implementation of generic software? Information systems researchers have differing views on this, some emphasizing the strengths of the generic and others the importance of contextual aspects. Contributing to this debate, Pollock and Williams have coined the term generification in order to describe how large vendors succeed in globalizing software packages through management by community, content and social authority. In this paper, we explore an approach that we call open generification, which extends Pollock and Williams' work in the sense that we acknowledge the need for and the feasibility of generic software, but propose an alternative model for the governance of it. Open generification is not about managing the community of users attached to a software package by homogenization or segmentation but aims at addressing the diverse needs of the community the software is expected to serve. Our empirical basis is a longitudinal study of the development of an open‐source health information system software (District Health Information software version 2), which is being used in more than 47 countries. Its success is attributed to a continuous interplay between generic and specific software and continuous cycles of embedding (implementing the global in the local context) and disembedding (taking local innovations into the global). We identify and discuss the contingent mechanisms of this interplay.     

TP_SDDT的设计与实现

ＴＰ＿ＳＤＤＴ是Ｔｕｒｂｏ ＰＡＳＣＡＬ环境中一个有效的软件工具，凡是与语法有关的软件开发工作，如语法分析，元级操作和部分求值等，均可利用ＴＰ＿ＳＤＤＴ来完成，本文介绍了ＴＰ＿ＳＤＤＴ的设计思想及实现技术。ＴＰ＿ＳＤＤＴ已在微机上实现。     

Programming with Divide-and-Conquer Skeletons: A Case Study of FFT

We demonstrate an approach to parallel programming, based on skeletons – parameterized program schemas with efficient implementations over diverse architectures. The contribution of the paper is two-fold: (1) we classify divide-and-conquer (DC) algorithms and provide a family of provably correct parallel implementations for a particular DC skeleton, called DH (distributable homomorphism); (2) we adjust the mathematical specification of the Fast Fourier Transform (FFT) to the DH skeleton and, thereby, obtain a generic SPMD program, well suited for implementation under MPI. The generic program includes the efficient FFT solutions used in practice – the binary-exchange and the 2D- and 3D-transpose implementations – as special cases.     

PowerPC 601 and Alpha 21064: a tale of two RISCs

A discussion is given on two RISC implementations: from Digital Equipment Corporation, the Alpha 21064, and from IBM/Motorola/Apple, the PowerPC 601. Both are superscalar implementations, that is, they can sustain execution of two or more instructions per clock cycle. Otherwise, these two implementations present vastly different philosophies for achieving high performance. The PowerPC 601 focuses on powerful instructions and great flexibility in processing order, while the Alpha 21064 depends on a very fast clock, with simpler instructions and a more streamlined implementation structure. These two RISC microprocessors exemplify contrasting, but equally valid, implementation philosophies. An overview is given of the instruction sets and the authors emphasize the differences in design: PowerPC uses powerful instructions so that fewer are needed to get the job done; Alpha uses simple instructions so that the hardware can be kept simpler and faster. The authors also discuss the pipelined implementations of the two architectures; again, the contrast is between powerful and simple     

Running repeatable and controlled virtual routing experiments

This paper describes an approach to perform reproducible performance tests on virtual routers, comparing different virtual routing architectures, different software versions and configurations. The presented approach is based on VRKit, a software tool that allows to build pre‐configured bootable virtual router images with the desired characteristics. Design decisions are described, and some usage examples are presented, showing how the tool can be used for research on virtual routing, facilitating performance comparison of various virtual router implementations. Copyright © 2013 John Wiley & Sons, Ltd.     

A reconfigurable computing framework for multi-scale cellular image processing

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100× for computationally expensive sub-problems and 10× for end-to-end applications compared to software implementations.     

Retargeting sequential image-processing programs for data parallel execution

New compact, low-power implementation technologies for processors and imaging arrays can enable a new generation of portable video products. However, software compatibility with large bodies of existing applications written in C prevents more efficient, higher performance data parallel architectures from being used in these embedded products. If this software could be automatically retargeted explicitly for data parallel execution, product designers could incorporate these architectures into embedded products. The key challenge is exposing the parallelism that is inherent in these applications but that is obscured by artifacts imposed by sequential programming languages. This paper presents a recognition-based approach for automatically extracting a data parallel program model from sequential image processing code and retargeting it to data parallel execution mechanisms. The explicitly parallel model presented, called multidimensional data flow (MDDF), captures a model of how operations on data regions (e.g., rows, columns, and tiled blocks) are composed and interact. To extract an MDDF model, a partial recognition technique is used that focuses on identifying array access patterns in loops, transforming only those program elements that hinder parallelization, while leaving the core algorithmic computations intact. The paper presents results of retargeting a set of production programs to a representative data parallel processor array to demonstrate the capacity to extract parallelism using this technique. The retargeted applications yield a potential execution throughput limited only by the number of processing elements, exceeding thousands of instructions per cycle in massively parallel implementations.