应用输入向量控制技术降低漏电功耗的快速算法

随着工艺的发展,为保证电路的性能和噪声容限必须降低阈值电压,这将导致漏电流呈指数增长,漏电功耗因而将逐渐超过动态功耗占据主导地位.CMOS的堆栈效应导致电路在不同向量下的静态功耗不同,因此在电路进入睡眠状态时使用输入向量控制技术是一种低功耗设计的有效方法,如何快速找到一个可降低电路漏电功耗的向量就成了问题的关键.介绍了一种在给定向量集合中查找低功耗向量的快速算法--基于概率传递的标记算法,并为此开发了一个事件驱动的门级组合电路仿真器.通过对ISCAS和龙芯处理器电路的实验结果表明,该算法同传统方法比较可以提高性能3.4倍,误差率仅约0.14%.     

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展，漏电流在深亚微米CMOS电路的功耗中变得越来越重要。因此，分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要，特别是在低功耗应用中。本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术。     

基于输入向量控制的衬底偏置技术面积优化方法

随着集成电路工艺进入纳米时代,VLSI漏电功耗迅速增加,增加了实时功耗管理系统的面积开销.为了大幅度减小反向衬底偏置(RBB)控制管的面积,对广泛应用的RBB优化漏电流技术提出一种新方法.基于双阈值CMOS电路设计,在输入最小漏电流向量的条件下,仅将反向偏置电压VRBB加到处于决定态的低阈值电压MOS管上,通过大幅度减小应用VRBB的晶体管数量来降低VRBB控制管的面积开销.在基于22nm工艺ISCAS85基准电路上与单纯RBB方法进行比较的实验结果表明,该方法以损耗27. 94%的漏电功耗优化效果为代价,降低了84. 91%的面积开销.     

组相联Cache中漏流功耗优化技术研究

随着集成电路制造工艺进入超深亚微米阶段,漏电流功耗在微处理器总功耗中所占的比例越来越大,在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化漏流功耗成为业界研究的热点.Cache在微处理器中面积最大,是进行漏流控制和优化的首要部件.本文提出了一种LRU-assist算法,利用既有的LRU信息,在保证处理器性能不受影响的前提下,cache的平均关闭率可达53%,大大降低了漏电流功耗.     

一种有效的低功耗扫描测试结构——PowerCut

扫描测试是超大规模集成电路测试中最常用的一种技术.但在扫描测试过程中,扫描单元的频繁翻转会引起电路中过大的测试功耗,这对电路测试提出了新的挑战.提出了一种新颖的低功耗全扫描结构--PowerCut,通过对扫描链的修改,加入阻隔逻辑,有效降低扫描移位过程中的动态功耗,同时加入控制单元,使电路在扫描移位过程时进入低漏电流状态,降低了电路的静态功耗.实验表明该结构在较小的硬件开销范围内有效地减小了扫描测试功耗.     

低功耗低电源线噪声纳米CMOS全加器

提出一种低功耗低电源线噪声的纳米CMOS全加器。采用电源门控结构的全加器来降低纳米CMOS电路的漏电功耗,改进了传统互补CMOS全加器的求和电路,减少了所需晶体管的数目,并进一步对休眠晶体管的尺寸和全加器的晶体管尺寸进行了联合优化。用Hspice在45nmCMOS工艺下的电路仿真结果表明,改进后的全加器电路在平均功耗时延积、漏电功耗和电源线噪声等方面取得了很好的效果。     

双阈值VLSI低测试功耗方法研究*

提出一种测试功耗优化的新方法,它通过阈值门电路调节和漏电流优化两种方法相结合来降低静态功耗。通过算法寻找电路的关键路径,去除伪路径,然后在关键电路上设置低阈值门电路,在非关键电路上设置高阈值门电路（不违反时序约束的前提下）,利用测试向量的无关位特性来调整测试向量和测试架构,达到降低漏电流的目的。通过以上两种途径,整体上达到功耗优化的结果,实验结果证实了本方法的有效性。     

无线传感器网络异步任务集双效节能延迟调度算法研究

深亚微米技术的发展,使得漏电功耗在CMOS电路总功耗中所占比重日益增大,传统的传感器节点CPU节能研究主要针对动态功耗,其能耗估计和优化方法已凸显局限.针对此问题,提出动态电压调节(DVS)和动态功耗管理(DPM)相结合的双效节能延迟调度算法.从相对截止期小于等于周期的异步实时任务调度出发,结合DVS技术,综合考虑动态功耗和漏电功耗的影响,在满足任务实时性的前提下,选取每个任务的CPU执行速度,以降低总能耗,并通过任务的延迟调度对CPU空闲时段加以合并,采用DPM方法使CPU在空闲时段有选择性的进入低功耗状态,从而进一步降低漏电能耗.仿真实验验证了该算法的有效性.     

电热分析研究的现状与展望

随着IC工艺进入纳米工艺时代,集成度与工作频率的增加,伴随性能提高的是不断增加的芯片功耗.高功耗的直接后果是产生了高供电电流和高功耗密度,而过大的供电电流降低了供电网络的供电电压;过大的功耗密度升高了内核温度,反过来又会增加电路时延,降低芯片的性能.所以在芯片设计中,必须对芯片功耗、供电网络、3D热分析进行快速而精确的电热分析;同时,漏电流功耗随工作温度升高而明显增加所造成的电热耦合效应,以及纳米工艺所带来的较大工艺参数变化,都提高了电热分析的难度.文中给出了电热参量(功耗、供电电压和内核温度)分析的重要性与研究现状,展望了纳米工艺下日益显著的工艺参数变化对电热分析所带来的挑战.     

基于多阈值技术的超低功耗电路设计

随着工艺进入深亚微米阶段,漏电流带来的静态功耗已经成为不可忽视的部分。多阈值CMOS技术是一种降低电路漏电流功耗的有效方法。本文在延迟不敏感异步电路中应用多阈值CMOS技术,该设计能显著的降低功耗,同时解决了同步电路存在的问题,比如sleep信号的产生,存储元件在sleep模式下数据丢失。这对深亚微米低功耗电路的设计具有一定的实际意义。     

Leakage current estimation of CMOS circuit with stack effect

Leakage current of CMOS circuit increases dramatically with the technology scaling down and has become a critical issue of high performance system. Subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakages are considered three main determinants of total leakage current. Up to now, how to accurately estimate leakage current of large-scale circuits within endurable time remains unsolved, even though accurate leakage models have been widely discussed. In this paper, the authors first dip into the stack effect of CMOS technology and propose a new simple gate-level leakage current model. Then, a table-lookup based total leakage current simulator is built up according to the model. To validate the simulator, accurate leakage current is simulated at circuit level using popular simulator HSPICE for comparison. Some further studies such as maximum leakage current estimation, minimum leakage current generation and a high-level average leakage current macromodel are introduced in detail. Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage current estimation methods are very accurate and efficient.     

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

     

蓄电池模拟装置主电路的拓扑及控制研究

蓄电池模拟装置在用电设备进行设计或检测时可以反复地、长时间地进行检测作业,可以提高效率并节约成本[1]。蓄电池模拟装置对于其功率电路的功能要求有：网侧可回馈电能,具有一定的动态跟随特性。本文设计了一种单相供电的网侧可回馈拓扑结构,一定程度上满足了蓄电池模拟装置对功率电路的功能要求。     

Leakage Current Optimization Techniques During Test Based on Don t Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,     

基于统计信息的Cache漏流功耗估算方法

随着工艺尺寸的缩小,漏流功耗逐渐成为制约微处理器设计的主要因素之一.Sleep Cache与Drowsy Cache是两种降低Cache漏流功耗的重要技术.基于统计信息的Cache漏流功耗估算方法(SB-CLPE)用于对Sleep Cache或Drowsy Cache进行Cache漏流功耗估算,根据该方法设计的Cache体系结构能够在程序执行过程中实时估算Cache漏流功耗.通过对所有Cache块的访问间隔时间进行统计,SB_CLPE可以估算出使用不同衰退间隔时Cache的漏流功耗,从而得到使Cache漏流功耗最低的最佳衰退间隔.实验表明,SB_CLPE对Sleep Cache的漏流功耗的估算结果与HotLeakage漏流功耗模拟器通过模拟获得的结果相比,平均偏差仅为3.16%,得到的最佳衰退间隔也可以较好吻合.使用SB_CLPE的Cache体系结构可以用于在程序执行过程中对最佳衰退间隔进行实时估算,通过动态调整衰退间隔以达到最优的功耗降低效果.     

基于改进CAF-WAS的绑定前硅通孔测试

硅通孔TSV发生开路故障和泄漏故障会降低三维集成电路的可靠性和良率,因此对绑定前的TSV测试尤为重要。现有CAF-WAS测试方法对泄漏故障的测试优于其他方法(环形振荡器等),缺点是该方法不能测试开路故障。伪泄漏路径思想的提出,解决了现有CAF-WAS方法不能对开路故障进行测试的问题。另外,重新设计了等待时间产生电路,降低了测试时间开销。HSPICE仿真结果显示,该方法能准确预测开路和泄漏故障的范围,测试时间开销仅为现有同类方法的25%。     

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

It is a well-known fact that test power consumption may exceed that during functional operation.Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor(CMOS)circuits during test has become a significant part of the total power dissipation.Hence,it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test,to increase test reliability and to reduce test cost.This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it,we propose techniques based on don't care bits(denoted by Xs)in test vectors to optimize leakage current in integrated circuit(IC)test by genetic algorithm.The techniques identify a set of don't care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector(MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.     

High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility

We propose a modeling methodology for both leakage power consumption and delay of basic CMOS digital gates in the presence of threshold voltage and mobility variations. The key parameters in determining the leakage and delay are OFF and ON currents, respectively, which are both affected by the variation of the threshold voltage. Additionally, the current is a strong function of mobility. The proposed methodology relies on a proper modeling of the threshold voltage and mobility variations, which may be induced by any source. Using this model, in the plane of threshold voltage and mobility, we determine regions for different combinations of performance (speed) and leakage. Based on these regions, we discuss the trade-off between leakage and delay where the leakage-delay-product is the optimization objective. To assess the accuracy of the proposed model, we compare its predictions with those of HSPICE simulations for both basic digital gates and ISCAS85 benchmark circuits in 45-, 65-, and 90-nm technologies.     

A novel high-density dual threshold GNRFET SRAM design with improved stability

We propose a novel single-ended static random access memory (SRAM) design with nine graphene nanoribbon FETs (9-GNRFET) in this paper. Single-ended has an impact on density, delays, static noise margin (SNM) and power consumption. The proposed model is implemented in HSPICE as a library for 16 nm GNRFET technology. This HSPICE-compatible compact model provides accuracy while maintain compactness, and make possible efficient circuit level simulations of futuristic GNRFET-based SRAM cells design. Simulations at low supply voltage of 0.325 V have shown that proposed cell provides power saving 4.8 × as compared to a supply voltage of 0.7 V. The half-select free technique provides bit interleaving architecture, consisting of error-free operations with V_DD down to 325 mV. The proposed architecture implemented in 16 nm low leakage GNRFET technology presents the scalability of these cells near threshed voltage region, which can significantly reduce power consumptions with 0.21µW. The proposed SRAM cell design is based on simulations and results are verified on GNRFET HSPICE-compact model. The proposed cell verified under process variation, and is demonstrated with write-assist, the impact of geometrical liability and adaptive supply voltage scaling.