网络传输控制的综合性能评价标准

在网络传输控制策略和算法的设计中，性能评价的标准是一个关键问题，不同的评价标准将导致不同的控制策略和算法设计。由于网络传输控制策略有着多方面性能的要求，如何同时满足多个性能目标是当前的研究难点，该文基于网络传输控制模型提出了一套对网络传输控制进行综合性能评价的有效标准，该标准综合考虑了网络整体性能、用户QoS要求和系统公平性等多维目标，作者对该标准进行了详细的讨论和分析，文中的综合性能标准可以广泛用于网络传输控制策略的性能评价和改进。     

网络数据包的协议分析算法设计与实现

为有效地监听网络状况和数据传输，截获网络传输的数据包，分析网络性能，排除网络故障，文中在以太网的基础上，通过对网络数据包的协议分析，殴计并实现了一个网络数据包的协议分析算法（PLA算法）。PLA算法可以有效地对网络中传输的数据包进行协议分析，解决了如何判别在网络上传输的数据包是什么类型的数据包，每一个数据包都用到了哪些协议。通过PLA算法对数据包的分析，可以使得流量统计和流量收费更加精确。     

一种CDMA2000链路层自适应重传算法

TCP协议应用在3G无线网络中时，其传输性能受到了无线网络物理层帧差错率的严重影响。链路层重传技术可以大大改善TCP数据传输性能因无线信道误码率大而下降的情况。主要研究了CDMA2000中链路层重传技术对无线TCP数据传输的影响，并结合TCP层重传超时机制，提出了一种新的自适应链路层重传算法，提高了TCP在无线链路的数据传输性能。最后对该算法进行仿真，验证了此算法可以显著提高TCP吞吐率。     

基于传输时延预测的多路径并发传输数据分配算法

针对多路径并发传输模型的整体性能在路径性能存在差异时会急剧下降的原因进行分析,给出了获取通信路径传输时延的有效评估方案,并在此基础上提出了一种基于传输时延预测的多路径并发传输数据分配算法.该算法通过获取和预测数据块在各条路径上引入的传输时延,以按序到达为目标对多路径并发传输模型发送回合内和发送回合间的数据分配过程进行优化,能够有效地减少路径传输性能差异对多路径并发传输模型整体性能带来的影响.分析和实验结果表明,该算法相对于默认的轮询数据分配算法能够取得较好的运行性能.     

网络数据包的协议分析算法设计与实现

为有效地监听网络状况和数据传输,截获网络传输的数据包,分析网络性能,排除网络故障,文中在以太网的基础上,通过对网络数据包的协议分析,设计并实现了一个网络数据包的协议分析算法(PLA算法)。PLA算法可以有效地对网络中传输的数据包进行协议分析,解决了如何判别在网络上传输的数据包是什么类型的数据包,每一个数据包都用到了哪些协议。通过PLA算法对数据包的分析,可以使得流量统计和流量收费更加精确。     

浅析网络传输控制的综合性能评价标准

随着科技的不断发展,互联网已经走进了千家万户当中,成为了居民生活中不可缺少的部分。综合性能评价标准是在网络传输控制当中相当重要的一个参考。这些评定标准与计算机的算法设计有着密切的关联,并且在控制策略上也需要相应的评定标准作为衡量度,这样才能够保证网络传输控制的整体质量。本文对网络传输控制进行了一个综合性的阐述,并对其综合性能评价标准进行了一个概括性的说明。     

噪声环境下IEEE 802.11 DCF的性能仿真及算法改进

在对噪声环境下IEEE 802．11 DCF性能进行仿真分析的基础上，提出了一种适应于无线噪声环境的DCF改进算法，该算法通过接收端反馈消息来区分因冲突和误码产生的数据包传输失败，并在发送端针对不同的传输失败原因分别采取不同的退避算法。仿真结果表明改进算法的性能优于DCF，饱和吞吐量比DCF最多能够提高103％。     

无线数据网络中基于博弈论方法的功率控制

功率控制是第3代移动通信网络中无线资源管理的一项关键技术，传统的功率控制主要考虑移动通信系统中的话音业务，设计了一个新的基于定价的效用函数，采用了博弈论的分析方法，提出了一个适用于无线数据网络的功率控制框架．证明了非合作功率控制博弈中存在惟一的纳什均衡，设计了一个分布的功率控制算法并证明了算法的收敛性．通过数值仿真来验证算法的性能，讨论了各个用户的传输特性和效用函数中定价因子对系统性能的影响，仿真结果表明用户可以用较低的传输功率获得较高的效用，算法具有较好的收敛性能。     

基于改进慢启动算法的大文件快速传输

针对传统TCP在当前网络环境下传输大文件性能较低的问题,对TCP传输协议中的慢启动算法部分进行了相应的研究与优化。根据标准慢启动算法存在的问题并结合高速网络以及大文件传输的性能特点,提出了一个具有网络状态感知能力的慢启动改进算法。改进算法主要优化了TCP拥塞窗口的增长策略,它实时地监测文件在传输过程中TCP报文段的往返时间（RTT）,并根据RTT的变化情况采用不同的窗口增长方式更新拥塞窗口;将改进算法部署在Linux网络模块中并分别在模拟网络环境和实际网络中进行测试。实验结果显示,改进算法能使发送窗口一直保持在一个较高的水平,实际数据传输速率和吞吐量均有了明显的提高。     

军事情报网格传输路径优化算法研究

如何有效地传输情报数据是军事情报网格研究的重要问题。将蚁群网格路由算法应用于军事情报网格的传输路径选择,提出一种带删除算子的蚁群网格路由优化算法。在该算法中,通过加入一个称为删除算子的变量,在整个情报传输网格中引入优胜劣汰机制,进行强制淘汰,同时对组合参数进行选择进化,以实现组网路径的有效选择。通过仿真实验证明该算法明显提高情报组网传输性能。     

Performance based design of high-level language-directed computerarchitectures

This paper is concerned with the analytical modeling of computer architectures to aid in the design of high-level language-directed computer architectures. High-level language-directed computers are computers that execute programs in a high-level language directly. The design procedure of these computers are at best described as being ad hoc. In order to systematize the design procedure, we introduce analytical models of computers that predict the performance of parallel computations on concurrent computers. We model computers as queueing networks and parallel computations as precedence graphs. The models that we propose are simple and lead to computationally efficient procedures of predicting the performance of parallel computations on concurrent computers. We demonstrate the use of these models in the design of high-level language-directed computer architectures.     

Progress and Challenges in High Performance Computer Technology

High performance computers provide strategic computing power in the construction of national economy and defense, and become one of symbols of the country＇s overall strength. Over 30 years, with the supports of governments, the technology of high performance computers is in the process of rapid development, during which the computing performance increases nearly 3 million times and the processors number expands over 10 hundred thousands times. To solve the critical issues related with parallel efficiency and scalability, scientific researchers pursued extensive theoretical studies and technical innovations. The paper briefly looks back the course of building high performance computer systems both at home and abroad, and summarizes the significant breakthroughs of international high performance computer technology. We also overview the technology progress of China in the area of parallel computer architecture, parallel operating system and resource management, parallel compiler and performance optimization, environment for parallel programming and network computing. Finally, we examine the challenging issues, ＂memory wall＂, system scalability and ＂power wall＂, and discuss the issues of high productivity computers, which is the trend in building next generation high performance computers.     

HDRA:一种基于历史寻径信息的分布式路由算法

直接互连网络已成为构建大规模并行系统的主流网络互连体系结构，路由算法对互连网络的通信性能和并行系统性能的发挥起着重要作用。针对静态互连网络，提出一种新的基于路由表查找技术的分布式路由算法HDRA，该算法有效地利用历史寻径信息，加快路由寻径速度，提高网络传输性能，而且算法设计简单，易于硬件实现。     

并行和分布式计算机监测系统的全局时钟设计

在分布环境下高度精确、可靠并且具有容错和检错能力的全局时钟是并行和分布式计算机监测系统中的一个极其重要的组成部分,它直接决定子分布环境下监测工作的精度以至最终的监测分析结果,本文以并行和分布式计算机监测系统ＭＳ－１为例,介绍了一种全局时钟设计方案,这种设计方案结合数字技术和锁相技术,采用容错和检错设计,具有理想的精度和可靠性以及很低的连接成本,事实上,该时钟的设计思想可适用于任何分布式实时系统。     

基于Linux的计算机集群系统的设计与实现

利用现成计算机构建由四台个人计算机组成的廉价、实用且性能优良的计算机集群。本研究设计是在有四台个人计算机组成的以太局域网内,建立一个基于Redhat9-Linux和MPI的集群计算环境,并在此基础上进行并行计算实验和性能测试。     

Distributed loop‐scheduling schemes for heterogeneous computer systems

Distributed computing systems are a viable and less expensive alternative to parallel computers. However, a serious difficulty in concurrent programming of a distributed system is how to deal with scheduling and load balancing of such a system which may consist of heterogeneous computers. Some distributed scheduling schemes suitable for parallel loops with independent iterations on heterogeneous computer clusters have been designed in the past. In this work we study self‐scheduling schemes for parallel loops with independent iterations which have been applied to multiprocessor systems in the past. We extend one important scheme of this type to a distributed version suitable for heterogeneous distributed systems. We implement our new scheme on a network of computers and make performance comparisons with other existing schemes. Copyright © 2005 John Wiley & Sons, Ltd.     

A communication system for distributed computations on a network of personal computers

This paper deals with a software system PCCOM which makes it possible to simulate a distributed memory environment for parallel computations by using a local area network of personal computers. This system consists of FORTRAN subroutines that can be used from application programs. Parallel computations may be performed on a network of personal computers under DOS or any other operating system. This software package simulates, partially, the widespread PVM (Parallel Virtual Machine) package which runs under UNIX. A simple example of an application is given here.     

Communication Benchmarking and Performance Modelling of MPI Programs on Cluster Computers

This paper gives an overview of two related tools that we have developed to provide more accurate measurement and modelling of the performance of message-passing communication and application programs on distributed memory parallel computers. MPIBench uses a very precise, globally synchronised clock to measure the performance of MPI communication routines. It can generate probability distributions of communication times, not just the average values produced by other MPI benchmarks. This allows useful insights to be made into the MPI communication performance of parallel computers, and in particular how performance is affected by network contention. The Performance Evaluating Virtual Parallel Machine (PEVPM) provides a simple, fast and accurate technique for modelling and predicting the performance of message-passing parallel programs. It uses a virtual parallel machine to simulate the execution of the parallel program. The effects of network contention can be accurately modelled by sampling from the probability distributions generated by MPIBench. These tools are particularly useful on clusters with commodity Ethernet networks, where relatively high latencies, network congestion and TCP problems can significantly affect communication performance, which is difficult to model accurately using other tools. Experiments with example parallel programs demonstrate that PEVPM gives accurate performance predictions on commodity clusters. We also show that modelling communication performance using average times rather than sampling from probability distributions can give misleading results, particularly for programs running on a large number of processors.     

Parallelized direct execution simulation of message-passingparallel programs

As massively parallel computers proliferate, there is growing interest in finding ways by which performance of massively parallel codes can be efficiently predicted. This problem arises in diverse contexts such as parallelizing compilers, parallel performance monitoring, and parallel algorithm development. In this paper, we describe one solution where one directly executes the application code, but uses a discrete-event simulator to model details of the presumed parallel machine, such as operating system and communication network behavior. Because this approach is computationally expensive, we are interested in its own parallelization, specifically the parallelization of the discrete-event simulator. We describe methods suitable for parallelized direct execution simulation of message-passing parallel programs, and report on the performance of such a system, LAPSE (Large Application Parallel Simulation Environment), we have built on the Intel Paragon. On all codes measured to date, LAPSE predicts performance well, typically within 10% relative error. Depending on the nature of the application code, we have observed low slowdowns (relative to natively executing code) and high relative speedups using up to 64 processors     

Programming methodology and performance issues for advanced computer architectures

This paper will describe some recent attempts to construct transportable numerical software for high-performance computers. Restructuring algorithms in terms of simple linear algebra modules is reviewed. This technique has proved very succesful in obtaining a high level of transportability without severe loss of performance on a wide variety of both vector and parallel computers. The use of modules to encapsulate parallelism and reduce the ratio of data movement to floating-point operations has been demonstrably effective for regular problems such as those found in dense linear algebra. In other situations it may be necessary to express explicitly parallel algorithms. We also present a programming methodology that is useful for constructing new parallel algorithms which require sophisticated synchronization at a large grain level. We describe the SCHEDULE package which provides an environment for developing and analyzing explicitly parallel programs in FORTRAN which are portable. This package now includes a preprocessor to achieve complete portability of user level code and also a graphics post processor for performance analysis and debugging. We discuss details of porting both the SCHEDULE package and user code. Examples from linear algebra, and partial differential equations are used to illustrate the utility of this approach.