MOS压控振荡器的设计

压控振荡器的作用是根据CP/LPF输出的包含参考信号与反馈信号频率或相位差的直流电压,输出对应频率的振荡信号。压控振荡器主要分为两大类：环形振荡器和LC振荡器。     

应用于无线通讯领域的新型振荡器

为了解决在深亚微米工艺下模拟射频电路在性能上的各种缺陷,该文论述了一种新型的LC振荡器,即数控振荡器(DCO),采用数字射频的方法来实现无线通讯的技术要求。这种新型的振荡器使用MOS变容管阵列来调节输出频率,通过使用数字Sig-ma-Delta技术,可以得到更精确的调频精度,而采用三种模式递进的工作方式使这种结构在工艺上更容易实现。     

应用于网络安全协处理器的真随机数产生器

介绍一款基于环形振荡器的真随机数产生器。电路使用固定频率时钟采样可控频率振荡器的输出,使用级间反馈随机改变可控频率振荡器的振荡频率。设计启动电路来保证环形振荡器快速起振,在使能信号无效时断开振荡电路以节省功耗。电路采用CMOS 0．18μm标准工艺实现,使用Hspice-RF仿真环形振荡电路的相位抖动以获得最优设计参数。仿真结果表明,电路在输出速率为1Gb／s时产生的随机序列具有良好的随机性,该设计可用于网络安全协处理器中。     

一种超低输入电压BOOST DC-DC的启动电路设计

以DC-DC升压电路的基本原理为出发点,结合电容的自举升压的特点,研究了一种低至0.48V超低电压输入的启动电路.为了降低电路的功耗,采用两个振荡器,频率高的振荡器的输出作为开始的升压控制,而频率相对低的振荡器的输出是作为升压电路开关管的控制.同时,振荡器均采用能在低电压情况下工作的环形振荡器,并且结构简单,易于集成.此电路基于BL0.6μm CMOS工艺模型设计,经仿真验证达到设计目标.     

LMDS射频单元锁相环式本振源设计

介绍了一种微波波段的固定频率振荡器的系统设计方案、主要电路单元设计以及系统:测试结果。采用分频式锁相环技术设计VCO锁相点频源来获得高稳定度、低相位噪声的输出信号。在LMDS射频收发单元中,该频率振荡器将作为一个提供11.776GHz稳定信号的本地振荡源。     

输出100W的SEPP超声发生器

小功率超声发生器被广泛用于小型清洗机、超声雾化加湿器以及雾化喷泉等设备中。目前,常用的超声发生器电路组成分为两大类:一类是用功率开关管(如常用的BU407之类)和LC振荡器产生超声波振荡;另一类是用时基电路555或反相器作为振荡信号源,放大后驱动功率输出级等。第一类电路简单,但频率稳定度较差,一旦超声输出功率偏离陶瓷换能器的固有谐振频率,则输出超声机械振荡频率将急速减小,其控制也较困难。一般若在自激振荡电路中用超声换能器本身的固有极间电容和谐振阻抗作为反馈元件,则可实现频率的自动跟踪。第二类电路的最大缺点是,一般简单电路中无法实现频率跟踪,当振荡频率改变时要手动跟踪,极为不便。     

MOSFET输出电容的非线性对振荡频率的影响

MOSFET的寄生参数会影响振荡器的性能指标。例如：漏极与源极之间的寄生电容（输出电容COSS）的存在会影响振荡器的频率。而且，COSS呈非线性特性。本文独具创新，以MOSFET的寄生电容作为振荡器的谐振电容。在这篇文章中，构造了包含非线性电容的电路等效模型，借助Matlab软件分析了非线性电容COSS对振荡频率的影响。分别获得了振荡频率随输出射频电压幅度变化和随直流电源电压变化的曲线。     

2.4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CIVICS负阻LC压控振荡器的相位噪声,介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0.35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3.3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc/Hz.该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路.     

适用于频率综合器的宽带低相噪VCO设计

针对频率综合器在宽调谐范围下相位噪声变差的问题,设计了一款适用于频率综合器的宽调谐范围低相位噪声的压控振荡器;采用180nm BiCMOS工艺,运用可变电容阵列和开关电容阵列实现宽调谐范围;通过加入降噪模块,滤除压控振荡器产生的二次谐波和三次谐波,增大输出振幅,降低相位噪声;并在压控振荡器输出端加入输出缓冲器,降低频率综合器其他器件对压控振荡器的影响;通过Cadence软件对压控振荡器进行仿真,仿真结果表明：调谐电压为0.3~3V,压控振荡器的输出频率范围为2.3~3.5GHz;当压控振荡器的中心频率为3.31GHz时,在偏离中心频率10kHz、100kHz和1MHz处的相位噪声分别为-93.21dBc/Hz,-117.03dBc/Hz,-137.41dBc/Hz,功耗7.66mW;在较宽的频率范围内,取得良好的相位噪声抑制,提高压控振荡器的噪声性能,满足宽带低相噪频率综合器的应用需求。     

2．4GHz低相位噪声CMOS负阻LC压控振荡器设计

为了有效降低工作于射频段的全集成CMOS负阻LC压控振荡器的相位噪声．介绍了利用电阻电容滤波技术对振荡器相位噪声的优化,并采用Chartered 0．35μm CMOS标准工艺设计了一款全集成CMOS负阻LC压控振荡器,其中心频率为2.4GHz,频率调谐范围达到300MHz,在3．3V电压下工作时,静态电流为12mA,在偏离中心频率600kHz处,仿真得到的相位噪声为-121dBc／Hz。该设计有效地验证了电阻电容滤波技术对相位噪声的优化效果,并为全集成低相位噪声CMOS负阻LC压控振荡器的设计提供了一种参考电路。     

Application of ultra wideband RF energy harvesting by using multisection Wilkinson power combiner

In this study, an ultra‐wide band (UWB) energy harvesting circuit was proposed using the Greinacher rectifier circuit. The circuit was designed with Wilkinson power combiner (WPC) for use at two different radio frequency signal inputs. To enable broadband operation, the multisection Chebyshev impedance matching technique was applied in the branches of the WPC circuit. The center frequency was selected 2.2 GHz in the design. In terms of the parameters of reflection, transmission and isolation, the WPC circuit operates in the 0.4 GHz‐3.4 GHz range and the percentage bandwidth has been calculated as 136%. In the designed Greinacher rectifier circuit, power conversion efficiency (PCE) was analyzed for different input powers. When load resistor selected as R = 1500 Ω, the PCE for the input power of 9 dBm was about 70%. The proposed circuit, where WPC and Greinacher rectifier circuits was used together for energy harvesting; was operated in the frequency ranges BW₁ = 0.4‐0.81 GHz, BW₂ = 1.54‐1.84 GHz, and BW₃ = 2.2 GHz‐2.89 GHz. As a power combining application, dual power inputs were applied to the WPC circuit with frequencies of 540 MHz‐1800 MHz, 540 MHz‐2450 MHz, 540 MHz‐2700 MHz, 800 MHz‐1800 MHz, 800 MHz‐2450 MHz and 800 MHz‐2700 MHz. Eventually, approximately 70.5% PCE and 1.65 V output voltage were obtained.     

UHFISM波段发射器的辐射功率和场强测试

工作在工业、科学及医疗(ISM)波段,频率范围为260MHz～470MHz的近距离无线通信已广泛用于遥控无钥匙门禁系统(RKE)、家庭安防和遥控装置。FCC规范中对260MHz～470MHz频率范围提出了场强指标要求,讨论了该指标与辐射功率及接收机所测得的典型指标间的关系。     

VHF宽带E类高效率功率放大器设计

使用ADS(Advanced Design System)软件仿真设计了基于28-V MOSFET器件的VHF频段30 MHz～80 MHz E类开关模式高效率功率放大器。输入端使用了宽带匹配,输出端通过开关改变后端的匹配电路和滤波器。电路实测:30 MHz～80 MHz输出功率3.2 W～7.1 W,效率从30 MHz的71.4%到80MHz的52.5%,并且具有优良的调幅线性度,可以将其应用到EER发射机。     

Eccentric annular slot patch antenna with frequency agility for UHF RFID reader applications

The design of a simple ultrahigh frequency RFID (radio frequency identification) reader antenna that can operate within the North America RFID band (902–928 MHz) is studied. To generate circular polarization (CP) radiation in this band, a novel method of loading two narrow open‐ended slots (slits) into an eccentric annular slot patch is proposed. To allow optimum impedance matching with enhanced CP bandwidth, the radiating patch is loaded to an L‐shaped ground plane. From the experimental results, the proposed antenna can yield an impedance bandwidth (10‐dB return loss) between 650 MHz to 1125 MHz, while good CP bandwidth (3‐dB axial ratio, AR) from 901 MHz to 930 MHz is also attained. Furthermore, gain level and efficiency of more than 7.8 dBic and 90%, respectively, were also measured. By simply removing one of the slits, this proposed antenna can also be modified to operate within the China (840–846 MHz) and European (865–868 MHz) RFID band.     

可自适应变频嵌入式微处理器核的设计

变频技术是一种非常实用的低功耗设计技术．本文设计了与MIPS32—4Kec指令兼容的嵌入式微处理器核SRISC—I，并内嵌锁相环（PLL）作为时钟发生电路，该微处理器核在软件控制下可自适应地改变工作频率．除正常的工作模式外，SRISC—I还支持空闲、体眠模式，可停止整个系统时钟及PLL的运行，有效地降低了功耗．仿真结果表明，在0．1SumCMOS工艺下，SRISCI最高频率达到250MHz，在PLL的控制下其工作频率可以以10MHz的步长改变．同时，给出了SRISC—I在不同频率下运行Dhrystone2．1程序的功耗，250MHz时为82．466m Watt，而在体眠模式下仅为28uWatt．     

1090MHz数据采集传输系统的实现

为探究1090MHz信道占用情况及信道内信号传输情况,设计开发了1090MHz数据采集传输系统。系统采用现场可编程逻辑门阵列(FPGA)与单片机(STM32)实现1090MHz信号的采集与传输;采用C++语言编写上位机软件,实现对数据采集部分的远程控制及数据的存取和显示。采集1090MHz频段的主要信号(ADS-B信号与二次雷达信号),初步观察信号的信道占用率及交织、受干扰情况,将数据有选择的保存至数据库进行后续分析。最后,在真实环境中采集1090MHz信号进行了测试,测试结果表明,该系统能够根据设置的命令参数采集传输1090MHz信道内的主要信号,实现了对信道实际状况及信道内信号传输情况的初步监测。     

FPGA-based implementation of a chirp signal generator using an OpenCL design

A novel approach to developing an FPGA-based chirp signal generator using high-level synthesis implementation is proposed. OpenCL, which is a framework used for high-level synthesis (HLS) methodologies, is employed instead of the Verilog/VHDL language to program FPGA. OpenCL has been used for FPGA programming, particularly in high-performance computing applications. Utilizing OpenCL for FPGA development reduces development time because of the high-level abstraction of the code. However, compared to Verilog/VHDL, standard OpenCL does not enable direct access to the FPGA's I/O. In this study, the FPGA needs to access the I/O pins to communicate with the DAC and generate the chirp signal. Thus, direct access to the FPGA I/O pin from the OpenCL environment is required. Therefore, a new OpenCL component is developed to enable the FPGA to communicate with the DAC, thus allowing data streaming to generate the chirp signal. This OpenCL component enables us to stream the data from the FPGA to generate the chirp signal. Here, we demonstrate that by using OpenCL implementation, the FPGA can generate an I/Q chirp signal efficiently. Moreover, the same OpenCL kernel can be employed to generate different bandwidths of the chirp signal without having to reprogram the FPGA. To demonstrate the capability of the system, we generated the I/Q chirp signal from 1 MHz to 5 MHz, 5 MHz to 10 MHz, 10 MHz to 15 MHz and 15 MHz to 20 MHz for a period of 10 µs.     

A miniaturized circularly polarized implantable RFID antenna for biomedical applications

A miniaturized circularly polarized implantable antenna operating at ultrahigh frequency band (902‐928 MHz) for radio frequency identification biomedical monitoring is first presented and experimentally validated in this article. The proposed antenna features a compact volume with a dimension of π × (6)² × 1.27 mm³ by employing an extended ring with meandered lines for size reduction. Moreover, adjusting the length of symmetrical meandered lines can introduce two orthogonal modes, which makes for good performance of circular polarization. Superb impedance matching between the chip and tag antenna is well implemented by applying a modified T‐match stub. In the simulation, the antenna achieves a ?10‐dB impedance bandwidth of 42 MHz (902‐944 MHz) and 3‐dB axial‐ratio bandwidth is 53 MHz (892‐945 MHz). Finally, the specific absorption rate is also calculated for human safety and the measured reading range reaches the maximum distance of about 87 cm.     

Linearly tapered meander line cross dipole circularly polarized antenna for UHF RFID tag applications

In this article, a circularly polarized antenna for ultra‐high frequency radio frequency identification (RFID) tag is presented. The circular polarization is realized by two orthogonal, unequal length linearly tapered meander line cross dipoles. The meander structure with capacitive tip loading is used for size miniaturization of the antenna. A modified T‐match network is employed to feed the cross dipole structure. The measured 10‐dB return loss bandwidth of the cross dipole antenna is 17 MHz (908‐923 MHz) and the corresponding 3‐dB axial ratio bandwidth is 6 MHz (912‐918 MHz). The overall size of the proposed antenna is 0.17λ₀ × 0.17λ₀ at 915 MHz. The maximum read range between the reader and the tag with the proposed antenna is 4.7 m larger than the analogous linearly polarized tag antenna due to the reduction in polarization loss between the tag and reader antennas. Thus, a maximum read range of 15.66 m with the gain of 1.28 dBic is achieved at 915 MHz.     

一种新型套筒天线宽频特性的HFSS仿真分析

针对传统套简单极子天线结构变量复杂、要做到3:1的频带宽度难的问题,利用电抗补偿方法设计了一款位于特殊接地铜管上的双层套筒偶极子天线,并利用HFSS软件对结构进行仿真分析,找到影响频带及反射特性的结构参数,通过软件自带的优化功能,对各个参数进行仿真优化,得到工作在800-960MHz,1710-1920MHz,2400-2483MHz频带范围内驻波系数低于1.5的实用套筒天线结构,包含目前移动通信所用频带:2G、3G和WLAN.天线在同一个结构上实现多频工作,且在各个频段内反射很小,节省了天线资源,利于系统集成.