基于SOI硅片研制新型P~+-I-N~+双注入磁敏差分电路

阐述基于SOI硅片制造新型P+ I N+双注入磁敏差分电路的设计原理和制造工艺。构成新型P+ I N+双注入磁敏差分电路的磁敏三极管的复合区采用MEMS中的各向异性腐蚀技术进行设置,给出了这种复合区的复合机理。实验结果表明:此种三极管具有磁灵敏度高、噪声低和可靠性高的特点。因此,由这种新型磁敏三极管构成的差分电路具有温度漂移小的优点。     

“磁传感器及其应用技术”讲座：第七讲 磁敏晶体管传感器（一）

磁敏晶体管分为磁敏二极管和磁敏三极管两类。它们都属于PN结型器件,其电特性随外施磁场的改变有显著的变化。磁敏二极管出现于60年代末期,磁敏三极管出现于70年代,现我国皆有生产与应用。由于它们具有体积小、灵敏度高(比霍尔器件约高百倍左右)、使用简单等优点,故作为磁传感器可用来检测磁场、电流、位移、液位、加速度、角度等参数,也可以用其构成无刷直流电机和各种非接触开关等。一、磁敏二极管磁敏二极管简称MD,目前可分为磁性整流器(CMD)和磁敏二极管(XMD)等。由于CMD的灵敏度     

“磁传感器及其应用技术”讲座：第八讲 磁敏晶体管传感器（二）

二、磁敏三极管磁敏三极管是继磁敏二极管后出现的一种新型的三端结型元件。它分为PNP型和NPN型两种。所用符号同晶体三极管只在旁边加一磁场符号×以示磁敏三极管。目前国内已有这种器件的生产,其中3CCM型硅磁敏三极管的主要参数见表3。3BCM型锗磁敏三极管的主要参数见表4,把两只3CCM型磁敏三极     

采用MEMS技术制造硅磁敏三极管

阐述了采用MEMS技术与反外延技术相结合在硅片表面制造具有矩形板状立体结构的硅磁敏三极管的设计原理、结构和工艺。结果表明 ,设计的硅磁敏三极管制造技术不但能与IC工艺相兼容 ,而且便于集成化 ,将有广泛的应用领域。     

应用磁敏Z元件直流无刷电机电子换相电路的研究

对磁敏Z元件的基本伏安特性、磁敏特性进行了实验测试,给出了实验结果,从内在微观结构和导电机理上对磁敏Z元件的特殊性质进行了分析.利用磁敏Z元件的特性,设计了用磁敏Z元件作位置传感器的直流无刷电机的电子换相电路,实现了在磁敏Z元件采集到的正弦信号驱动下对四个绕组有序选通的控制,并针对Z元件输出信号随温度漂移的现象进行了测试分析.     

三漏CMOS磁敏器件

采用矩形结构的霍尔元件作为磁敏电路中敏感部分的硅霍尔磁敏器件已相当成熟,但磁灵敏度不大,仅约10~2V/AT.因此探讨具有高灵敏度的磁敏器件,对于工艺相当成熟的硅材料来说仍然很有意义.从硅的MOS器件来看,早先由Gallagher和Corak提出用MOS表面的反型导电层做MOS霍尔元件,曾达到10~3V/AT的灵敏度.而后由Fry和Hoey提出用双漏MOS场效应晶体管做成灵敏度达10~4V/AT的磁敏元件.由于负载电阻大,稳定性较差,Popovic和Baltes又进一步用这种晶体管做成CMOS差分放大器结构形式,得到了有同样灵敏度且较稳定的磁敏器件.     

磁敏Z元件位移传感器的研究

研制出一种新型磁敏Z元件位移传感器。并对磁敏Z元件的伏安特性和磁敏特性进行研究,给出了实验结果。设计了由信号采集、数据处理以及数字显示等电路构成的系统,实现了位移量的测量。由于Z元件的特殊性质,其应用电路较为简单。     

低温漂巨磁阻抗磁敏开关的设计

Fe73.5Cu1Nb3Si13.5B9非晶合金薄带在540℃下17.8 MPa拉应力退火后具有宽平台和陡峻下降沿的巨磁阻抗特性,据此研制了一款新型磁敏开关。文中介绍了磁敏材料的GMI特性及磁敏开关的电路设计原理,对磁敏开关的磁场和温度特性进行了测试,结果表明:该磁敏开关的重复性好,迟滞误差小,温漂低。     

3CCM型硅磁敏三极管可靠性的试验研究

3CCM型硅磁敏三极管长期贮存寿命试验和加热老化试验表明,它的零场集电极电流相对时漂概率分布极值在1％以内,且时漂概率分布与老化时间呈对数关系。     

扩散硅压力传感器性能优化研究

本文论述了实现扩散硅压力传感器性能优化的一些技术措施、设计原理和工艺技术.采用矩形双岛硅膜结构等新型微机械结构可提高灵敏度和精度并实现过压保护;通过改善工艺并进行表面钝化、改进封装工艺与结构等可改善稳定性;用恒压源及三极管补偿法和等效电阻最佳耦合法可对其灵敏度、零位温度系数进行补偿;采用各向异性腐蚀工艺技术可实现集成化生产.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

用巨磁电阻式位置传感器测量材料的杨氏模量

介绍了一种新型高灵敏度巨磁电阻式传感器的工作原理和使用方法,并利用它测量了钢片的杨氏模量。实验结果表明：用该巨磁电阻式传感器测量杨氏模量,测量方法实用性强,精确度较高。     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

硅悬臂梁脉象传感器温度补偿

阐述了采用硅悬臂梁制造的脉象传感器结构、设计和温度补偿原理。实验结果表明:补偿后的传感器具有灵敏度高、稳定性好,线性度为1%FS(0~5 N),重复性为0.5%FS,灵敏度为50 mV/N。给出的温度补偿晶体管对该脉象传感器的灵敏度温度漂移补偿效果好,有推广应用前景。     

Hardware Security in the Dark

The increasing transistor count on a single chip provides an unprecedented amount of resources for chip designers. Unfortunately, the power consumed by each transistor does not shrink similarly, decreasing the amount of transistors that can be on simultaneously. This utilization wall leaves a growing percentage of transistors dark, or powered-off, as the chip cannot (a) provide the necessary current or (b) maintain a low operating temperature. To account for dark silicon, the computer architecture community has begun taking advantage of the wealth of available transistors to design efficient, time-sharing systems, often through specialized architectures. Meanwhile, security is quickly becoming a first-tier design constraint, increasing the need for hardware security mechanisms, in order to maintain high levels of availability and to detect and protect from intrusion. As we move into the many-core environment, many of these security mechanisms will need to be integrated on-chip. In a chip-multiprocessor environment, security will be necessary as multiple programs or users are sharing resources, thus facilitating attacks. In both a single-user and multiple-user environment, designers can build specialized hardware to provide support for security functions, such as authenticity, cryptography, and intrusion detection. In this paper, we survey current hardware security trends and provide insight on how future chip designs can leverage dark silicon for more secure designs. We provide preliminary designs and discuss future challenges and opportunities in dark silicon security. The merging of hardware security and dark silicon will facilitate efficient, fast, and secure designs.     

A 550‐PPI LCD using 1.5 µm channel width LTPS TFTs with low frame rate driving

A 550 PPI low‐temperature polycrystalline silicon thin‐film transistor liquid‐crystal display has been developed. Shrinkage of the channel width of pixel thin‐film transistor together with thinner insulator for the storage capacitor allows high display quality in terms of vertical cross‐talk and flicker. Thirty hertz frame rate driving is implemented to offer low power while keeping high display quality.     

Clocked control scheme of separating TFTs for a node‐sharing LTPS TFT shift register with large number of outputs

This paper proposes the node‐sharing low‐temperature poly‐silicon (LTPS) thin‐film transistor (TFT) shift register with the clocked control scheme that completely turns separating TFTs off during the bootstrapping period to compensate for internal resistive and capacitive loads. The fluctuation is also addressed by adding pull‐down TFTs or raising the low level of the control signal.     

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Abstract— P‐type low‐temperature (450°C) polycrystalline‐silicon thin‐film‐transistor circuits for peripheral driver integration in active‐matrix displays are proposed and verified. A low‐voltage (5 V) driven poly‐Si scan driver is designed by employing a level shifter and shift register. A source driver for six‐bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D') without an output voltage loss. A new source‐follower type analog buffer is developed and exhibits a small offset deviation regardless of the V_TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p‐type panel integration.     

基于InSb-In磁阻元件的液体流量计的设计

设计了一种用InSb-In共晶体薄膜磁阻元件制作而成的液体流量计,该流量计中的转动涡轮由磁钢材料制作,当转动的涡轮叶片靠近InSb-In共晶体薄膜磁阻元件时引起其阻值的变化,进而产生交变信号。经过对信号的处理,单片机进行计数,可以得到瞬时流量和累积流量。本流量计采用西6mm管径设计,实验中采用自来水作为被测液体,每脉冲代表液体流量为0．8776mL,其有效测量量程为0．05—0．5m^3／h,测量误差在±0．4％左右,能满足低流速测量工业现场的使用要求,并能降低制造成本。