车车通信中通信模式选择与资源分配算法

在城市轨道交通列车控制系统中,车车（train-to-train,T2T）通信是利用列车之间直接通信来保障列车安全、高效运行的一种通信模式。与传统的车地（train-to-ground,T2G）通信模式相比,基于T2T通信的系统可以简化系统结构,降低系统成本,提高列车运营效率。为保证通信链路信噪比的同时最大程度地提高整个系统的信道容量,研究了T2G通信模式与T2T通信模式共存情况下的联合通信模式选择和资源分配问题。提出了一种通信模式选择算法,其目的是使列车能够自适应地选择具有更好通信质量的通信模式。在通信模式选择的基础上,提出了一种基于拉格朗日对偶函数法的资源分配算法,该算法可获得列车在不同通信模式下的最佳传输功率。仿真结果表明,相比于其他资源分配算法,所提算法能明显提升系统的信道容量。     

基于量子粒子群算法的可重构系统软硬件划分

针对软硬件协同设计中软硬件划分的这个关键问题,提出了一种基于量子粒子群算法的动态可重构系统软硬件划分的算法;首先使用有向无环图对嵌入式系统建模,得到软硬件划分优化系统的目标函数;然后通过采用自适应的量子旋转角调整策略以及引入量子变异操作,有效避免搜索过程陷入局部最优,提高搜索效率;对比实验结果表明本文算法对解决软硬件划分问题的有效性;文章算法不但能够以更快的搜索速度得到软硬件划分结果,并且得到划分结果更优,是一种具有较高性能的划分方法.     

无线视频通信中信道自适应差错控制策略的研究

针对无线视频通信中现有的差错控制方法的缺点和局限性，根据无线信道高误码率和高时变性的特点，提出一种基于反馈的信道自适应差错控制策略．根据反馈信号预测未来信道的状态，自适应地调整冗余信息值，优化无线视频通信系统的传输效率，使其在稳定性、功率消耗和传输效率之间达到有效的折衷．仿真结果表明，该方法能有效地提高无线视频通信系统的传输效率，尤其在无线信道误码率变化剧烈的情况下，效果更加明显．     

流星余迹通信自适应变速系统性能分析与仿真*

为提高流星余迹通信的数据通过量,根据流星余迹通信信道的指数性衰落特性,提出了一种基于信噪比估计的自适应变速方法.该方法根据估计流星信道信噪比的变化情况,动态地改变系统的比特速率,实现自适应变速,从而有效提高了流星信道利用率,实现数据的可靠传输.仿真结果表明,在相同信道条件下,该系统的数据通过量比固定速率传输系统提高2～4 倍,是一种有效而可靠的通信方法.     

遗传退火算法在软硬件划分中的应用

针对基于IP核的软硬件划分组合问题,提出一种改进的自适应最优保存的遗传退火算法。将最优保存遗传算法和模拟退火算法相结合,把循环策略应用到混合算法中,并在变异概率中引入自适应的概率变化,自适应地保存最优个体,有效地解决了这2种算法的早熟现象和时间问题。仿真实验表明该算法有效地解决了软硬件划分问题,具有较强的搜索和跳出局部最优的能力。     

IPC研究及其在工控软件中的应用

为工控软件选择合适的进程通信方式,能够迅速准确地监测现场数据,有效地控制生产过程.通过大量实验分析找出了适合不同监测点的进程通信模式,并对加快工业控制软件响应速度从数据冗余、信息承载量和例外报告入手提出了三种优化传输效率方案,从而达到快速响应的目的.     

基于同频相位载波均值算法军用通信优化仿真

研究军用通信设备在受到干扰情况下的优化通信问题.针对军用通信信道中依靠广播特性完成通信,其它发射机的同频干扰信号会错误地对齐到通信设备中,对同一个接收信号空间的子空间形成干扰.传统的军用通信方法在这种干扰的环境下,会形成频率干扰,造成通信效率下降.为此,提出了一种基于同频信号相位载波均值算法的军用通信优化方法,可以根据分组信息长度与缓冲阈值的关系进行信道选取,建立军用通信模型.利用同频信号相位载波均值算法进行抗干扰处理,从而提高军用通信的效率.实验结果表明,这种算法能够有效提高军用通信效率.     

基于隐马尔可夫模型的通信态势估计方法

针对移动通信过程中通信态势无法被预知导致的服务效率较低问题,给出一种基于隐马尔可夫模型的区域通信态势估计方法。根据不同时间点的通信行为特征具有差异性的特点,对通信行为按不同的时间段进行划分,并自适应地给出具体的划分算法,即遗传法或遍历法。挖掘终端行为发生时间、地点以及通信行为之间的内在联系,构建隐马尔可夫模型,利用维特比译码算法对区域内终端位置及通信行为进行估计。仿真结果表明,当模式特征值取0.8时,该方法的终端位置预测成功率在73%左右,通信行为预测成功率在75%左右。     

一种高效的虚拟网络结构

弹性资源需求是云计算的关键特征,它需要系统支持自适应的虚拟网络配置管理机制,以满足云计算服务中虚拟资源的动态组合要求。本文提出了一种高效的虚拟网络结构,能够根据虚拟资源的动态分配状态,在网络层面建立相应的应用群组,提高组内资源的通信效率。不仅如此,本文提出的虚拟网络结构还能根据虚拟资源在物理平台上的实时分布状态,选择不同的信息传送机制,保证虚拟资源之间的高性能通信。     

基于EDA的嵌入式系统软硬件划分方法

针对嵌入式系统软硬件协同设计中的软硬件划分问题,提出了一种基于分布估计算法的解决方案,通过将算法映射到一般结构Gauss网络上,提高了算法的稳定性和搜索效率.结果表明,该算法有效地解决了软硬件划分问题.     

一种基于SoC平台设计的AVS解码器软硬件分区结构

视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。该文针对AVS标准的算法和解码实现复杂程度,根据软硬件协同设计思想提出了一种结构划分合理的AVS高清视频解码器软硬件分区结构。根据AVS算法的特点该结构将宏块层以上部分的元素解析划归到软件解码中,将宏块层解码划为硬件处理。经验证,该结构设计可实现AVS高清码流解码,并在C语言编写的硬件平台仿真程序中得以实现。     

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).     

基于改进0-1动态规划的软硬件划分算法研究*

软硬件划分已被证明是NP完全问题,大多数研究主要集中在寻找各种快速的近似算法,常见的有爬山法、遗传算法、模拟退火、禁忌搜索等.这些算法大多只能处理小规模问题,而且是单纯从算法角度来研究软硬件划分问题,并没有考虑系统成本.以软硬件协同函数库为统一抽象模型,将系统执行时间、系统成本以及硬件面积等因素融入到0-1动态规划算法...     

ECC专用指令处理器软硬件协同设计

提出了一种专用指令处理器的软硬件协同设计方法,该方法可以在设计的早期阶段对处理器进行系统探索和验证.根据椭圆曲线密码算法的特点,并按照专用指令处理器的设计原则,以椭圆曲线密码运算基本操作及运算存储特性为基础,设计了超长指令字ECC专用指令处理器的指令集结构模型.根据处理器的指令集结构模型,以指令模拟器为基础,搭建了处理器的软硬件协同验证平台,从系统设计、RTL描述和FPGA硬件原型3个不同层次对处理器进行了验证.     

低速率语音编解码专用处理器设计

本文给出一种基于编码速率600bps的高质量声码器算法的专用处理器设计。介绍了语音编解码算法原理,专用处理器的体系结构,汇编器的开发和算法的移植。采用软硬件协同设计的方法,大大降低了算法的存储复杂度和运算复杂度,并在电路中验证了声码器地正确性。     

Parallel Programming of Multi-processor SoC: A HW–SW Interface Perspective

For the design of classic computers the parallel programming concept is used to abstract HW/SW interfaces during high level specification of application software. The software is then adapted to existing multiprocessor platforms using a low level software layer that implements the programming model. Unlike classic computers, the design of heterogeneous MPSoC includes also building the processors and other kind of hardware components required to execute the software. In this case, the programming model hides both hardware and software refinements. This paper deals with parallel programming models to abstract both hardware and software interfaces in the case of heterogeneous MPSoC design. Different abstraction levels will be needed. For the long term, the use of higher level programming models will open new vistas for optimization and architecture exploration like CPU/RTOS tradeoffs.     

HW/SW co-design for public-key cryptosystems on the 8051 micro-controller

It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW co-design solution for RSA and Elliptic Curve Cryptography (ECC) over GF(p) on a 12 MHz 8-bit 8051 micro-controller. The hardware coprocessor has a Modular Arithmetic Logic Unit (MALU) of which the digit size (d) is variable. It can be adapted to the speed and bandwidth of the micro-controller to which it is connected. The HW/SW co-design space exploration is based on the GEZEL system-level design environment. It allows the designer to find the best performance-area combination for the digit size. As a case study of an FPGA prototyping, 160-bit ECC over GF(p) (ECC-160p) was implemented on Xilinx Virtex-II PRO (XC2VP30). The results show that one point multiplication takes only 130 ms including all communications between the 8051 and the coprocessor. The performance is 40 times faster than the most optimized SW implementation on a small CPU in literature. This is achieved by the HW/SW co-design exploration in order to find the optimized digit size of the MALU. On the other hand, the design of ECC-160p maintains a high level of flexibility by using coprocessor instructions. Our proposed architecture proves that HW/SW co-design provides a high performance close to ASIC solutions with a flexible feature of SW even on a small CPU.     

A metaprogrammed C++ framework for hardware/software component integration and communication

With the ever growing complexity of System-on-Chip design, a considerable effort has been made to introduce higher levels of abstraction and to integrate high-level synthesis solutions to the design flow. In such design flows, a uniform communication interface is needed to enable high-level implementations of SoC components regardless of whether they are compiled as software running on a processor or synthesized to dedicated hardware IPs. This paper addresses this issue and proposes a component communication framework that defines an object-oriented remote call mechanism which allows transparent communication across hardware/software boundaries. The proposed framework relies on C++ static metaprogramming techniques to efficiently abstract communication between components implemented using high-level C++. We also define a portability layer that enables the migration of designs throughout different hardware platforms, operating systems, and tools. We assessed the performance and area footprint of our communication infrastructure through the implementation of a voice processing pipeline on top of a Network-on-Chip based architecture. Our results, when compared to previous related works with the same set of capabilities, show that our mechanisms yield small overhead in terms of software memory (up to 64% smaller), FPGA resources (up to 40% smaller), and hardware/software communication latency (up to 51% smaller).     

一种基于DQCGA算法的软硬件动态划分方法

软硬件划分是嵌入式系统设计的高层抽象环节中最重要的关键步骤之一.在某些数据相关的应用领域中,划分环境是动态变化的,因此我们提出了一种解决动态软硬件划分的方法.这种方法基于一种名为DQCGA的演化算法.DQCGA算法受自然界中对称和互补机制的启发,操纵一对互补的概率向量来适应动态变化的环境.我们系统地完成了建模,动态环境定义等环节,然后通过和已有方法的比较,有针对性地设计了实验.试验结果很好地证明了该方法对于解决软硬件划分问题的可行性和有效性,并且较之以往的方法有着更好的表现.