低功耗15Mbps光电耦合器

东芝公司（ToshibaCorporation，推出了将15Mbps高速通信与低功耗相结合的“TLP2361”和“TLP2161”光电耦合器。批量生产定于2013年8月开始。     

一种基于IA-64的并行架构的研究

同时多线程（SMT）能在同一时钟周期执行不同线程的指令,同时开发了指令级并行（ILP）和线程级并行（TLP）。显式并行指令计算（EPIC）关注于编译器和硬件的相互协作。在本文中,我们设计和实现了一套并行环境,其中包括并行编译器OpenUH和基于IA-64的同时多线程体系结构EDSMT,并通过NAS并行测试程序作出了性能评测。     

软件流水的低功耗编译技术研究

对具有可动态独立调整运行频率/电压的多功能部件配置结构M,基于全局调度的循环依赖关系,使用ILP形式化框架,研究了对给定循环L进行动态频率/电压调整的低功耗软件流水调度的编译优化技术.提出了一种合理而有效的低功耗最优化软件流水调度方法,使其在运行时保持性能不变而消耗的功耗/能量最小.     

低功耗15Mbps光电耦合器

东芝公司(Toshiba Corporation,推出了将15Mbps高速通信与低功耗相结合的"TLP2361"和"TLP2161"光电耦合器。批量生产定于2013年8月开始。这些产品融合了东芝的原始红外线LED。该LED的高输出和可靠性可确保低输入电流工作,并使阈值输入电流较同类产品1降低大约54%。这种LED在高环境温度下拥有稳定输出,     

全局指令调度综述

指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。然而基本块通常很小,因而潜在的ILP也很小。随着芯片设计技术的发展,现代的处理机所包含的资源却越来越丰富。指令调度只有跨越基本块的边界(即全局指令调度)才能够充分发挥处理机潜在的和程序中固有的ILP。全局指令调度可划分为有环和无环两种。该文介绍了无环全局指令调度的几种影响力较大的算法。同时还简单介绍了有关全局指令调度的新的热点。     

一种低功耗八位MCU的设计与实现

介绍了一个低功耗八位微控制器的结构设计，选择了适当的微控制器的体系结构和指令流水线，简化了电路结构，大大减少了执行每条指令所需要的时钟数。另外，通过对算术逻辑单元进行优化设计，节省了系统的资源，减小了电路的寄生电容，从而达到了降低功耗的设计目标。     

选择策略对遗传归纳逻辑程序设计收敛性能的影响

采用遗传算法（GA）作为归纳逻辑程序设计（ILP）的搜索策略，可以提高ILP方法的鲁棒性和适应性，文章简要叙述了对作者提出的遗传归纳逻辑程序设计（GILP）算法作的改进，测试了选择策略对GILP算法收敛性能的影响，采用不同的选择策略不会影响算法的最终收敛结果，但会产生不同的选择压力，导致算法具有不同的收敛速率。     

单片机低功耗技术及应用

介绍单片机的低功耗设计技术特点及单片机应用系统中的低功耗设计要注意的几个问题,并列举了充分利用片内资源实现低功耗及C语言源程序。     

ILP多级复接自适应同步技术

结合实用化综合业务接入系统内部标签分组(ILP)在系统中的传输与处理结构,针对ILP在系统中基于多总线背板传输的时延与同步问题,提出了一种实用的“一对多”背板总线传输的自适应bit位同步和ILP包同步解决方案和实现方法,并讨论了空闲字节(IdleBytes)对业务承载效率的影响。     

FPGA设计中的低功耗解决方案

本文讨论了FPGA设计中的低功耗问题。从功耗的产生原因和相关公式着手。针对静态和动态的主要功耗提出了相应的解决方案。以Actel eX系列以及SX／SX—A系列器件为例，阐述了器件的结构特点与低功耗的设计技巧。     

IA-64的并行架构及其寄存器文件

同时多线程能在同一时钟周期执行不同线程的指令,并且指令级并行和线程级并行。显式并行指令计算关注于编译器和硬件的相互协作。寄存器文件的设计在高性能处理器设计中十分重要,寄存器栈和寄存器栈引擎是提高其性能的重要手段。该文设计和实现一套并行环境,其中包括并行编译器OpenUH和基于IA-64的同时多线程体系结构EDSMT,实验表明,该并行架构适用于大多数并行应用,针对NAS的并行测试程序,该架构相对于SMTSIM平均有12.48%的性能提升。     

Exploring the performance limits of simultaneous multithreading for memory intensive applications

Simultaneous multithreading (SMT) has been proposed to improve system throughput by overlapping instructions from multiple threads on a single wide-issue processor. Recent studies have demonstrated that diversity of simultaneously executed applications can bring up significant performance gains due to SMT. However, the speedup of a single application that is parallelized into multiple threads, is often sensitive to its inherent instruction level parallelism (ILP), as well as the efficiency of synchronization and communication mechanisms between its separate, but possibly dependent threads. Moreover, as these separate threads tend to put pressure on the same architectural resources, no significant speedup can be observed. In this paper, we evaluate and contrast thread-level parallelism (TLP) and speculative precomputation (SPR) techniques for a series of memory intensive codes executed on a specific SMT processor implementation. We explore the performance limits by evaluating the tradeoffs between ILP and TLP for various kinds of instruction streams. By obtaining knowledge on how such streams interact when executed simultaneously on the processor, and quantifying their presence within each application’s threads, we try to interpret the observed performance for each application when parallelized according to the aforementioned techniques. In order to amplify this evaluation process, we also present results gathered from the performance monitoring hardware of the processor.

The Impact of Speculative Execution on SMT Processors

By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due to incorrect control speculations, a significant number of these in-flight instructions are discarded from the pipelines of SMT processors (which is a direct consequence of these pipelines getting wider and deeper). Although increasing the accuracy of branch predictors may reduce the number of instructions so discarded from the pipelines, the prediction accuracy cannot be easily scaled up since aggressive branch prediction schemes strongly depend on the particular predictability inherently to the application programs. In this paper, we present an efficient thread scheduling mechanism for SMT processors, called SAFE-T (Speculation-Aware Front-End Throttling): it is easy to implement and allows an SMT processor to selectively perform speculative execution of threads according to the confidence level on branch predictions, hence preventing wrong-path instructions from being fetched. SAFE-T provides an average reduction of 57.9% in the number of discarded instructions and improves the instructions per cycle (IPC) performance by 14.7% on average over the ICOUNT policy across the multi-programmed workloads we simulate. This paper is an extended version of the paper, “Speculation Control for Simultaneous Multithreading,” which appeared in the Proceedings of the 18th International Parallel and Distributed Processing Symposium, Santa Fe, New Mexico, April 2004.     

Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture

Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscalar processors. One promising method of exploiting TLP is Dynamic Speculative Multithreading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions. This paper introduces Cascadia, a D-SpMT multicore architecture that provides multigrain thread-level support and is used to evaluate the performance of several benchmarks. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multithread. This paper also discusses the relationships that loops have on one another, in particular, how loop nesting levels can be extended through procedures. In addition, a detailed study is provided on the effects that thread granularity and interthread dependencies have on the entire system.     

低功耗多线程编译优化技术

提出了在多线程体系结构中通过降低执行频率有效减小功耗的理论模型和方法.首先研究识别可降频运行的线程的计算模型和降频因子的计算,然后给出在编译过程中基于对应用程序行为的分析,结合线程划分的低功耗编译优化算法和实现策略.该模型和方法可用于具有执行频率可动态调整的多处理器类多线程体系结构,既可开发TLP(thread level parallelism),又可有效减小功率消耗.     

A continuation-based noninterruptible multithreading processor architecture

Current trend of research on multithreading processors is toward the chip multithreading (CMT), which exploits thread level parallelism (TLP) and improves performance of softwares built on traditional threading components, e.g., Pthread. There exist commercially available processors that support simultaneous multithreading (SMT) on multicore processors. But they are basically based on the conventional sequential execution model, and execute multiple threads in parallel under the control of OS that handles interruptions. Moreover, there exist few languages or programming techniques to utilize the multicore processors effectively. We are taking another approach to develop a multithreading processor, which is dedicated to TLP. Our processor, named Fuce, is based on the continuation-based multithreading. A thread is defined as a block of sequentially ordered instructions which are executed without interruption. Every thread execution is triggered only by the event called continuation. This paper first introduces the continuation-based multithread execution model and its processor architecture then gives multithreaded programming techniques and the continuation-based multithreading language system CML. Last, the performance of the Fuce processor is evaluated by means of the clock-level software simulation.     

基于EPIC的同时多线程处理器取指策略

EPIC硬件简单，同时多线程易于开发线程级并行，在EPIC上实现同时多线程可以结合二者的优点。取指策略对同时多线程处理器的性能有重要影响。该文介绍了几种有代表性的超标量同时多线程处理器取指策略，分析了这些策略在EPIC同时多线程处理器上的适用性，提出了一种新的适用于EPIC的取指策略SICOUNT。分析表明SICOUNT策略可以充分利用EPIC软硬件协同的优势，在选择取指线程时使用编译器所提供的停顿信息，能更精确地估计各个线程的流动速度，使取出指令的质量更高。     

多核、多线程处理器的低功耗设计技术研究

随着微处理器设计技术和半导体制造工艺的进步，芯片的规模和复杂度急剧增大，超高的功耗密度对系统稳定性造成很大影响，功耗壁垒已经成为提升微处理器性能的最大障碍。本文介绍了低功耗设计的基本原理、研究内容、设计方法，分析了CMP和SMT体系结构的功耗需求和特性，讨论了不同的功耗优化策略在两种体系结构下的适用程度以及对性能造成的影响。针对多核、多线程体系结构，着重从系统级、结构级和电路级等不同抽象层次对典型的功耗优化技术做了讨论。最后，展望了未来微处理器低功耗设计技术的发展趋势。     

极高集成度的处理机体系结构：未来计算机技术基础

在国际上，计算机学者在讨论下一代的处理机体系结构和未来的计算机技术。因为微电子工艺的迅速发展，已有可能在一个芯片上集成１０亿个晶体管。这样的极高的集成度（ＥＬＳＩ），为计算机体系结构设计者开辟了一个宽广的技术领域和思想空间，容许我们设计出崭新的处理机和计算机芯片。本文综述了目前美国认为有前途的四种所谓ＢｉｌｉｏｎＴｒａｎｓｉｓｔｏｒｓｏｎＣｈｉｐ的体系结构：即单个功能很强的处理机（Ｕ－ＮＩＰＲＯＣ），并发的多线程处理机（ＳＭＴ），片上多处理机系统（ＣＭＰ），和智能随机存储器（ＩＲＡＭ）。这四种体系结构，将充分利用片上指令级并行性ＩＬＰ和线程级的并行性，或充分利用片上数据交换的极高频宽，或充分利用ＣＰＵ和存储器之间的高速频带总线。而这种１０亿晶体管的芯片，可使单片的峰值速度达到１６０亿次／秒。这对未来的计算机技术会带来极其深刻的影响。在这种芯片设计中，体系结构设计者还要十分注意微电子工艺在极高集成度中的一些特殊问题。