Overhead in FORTRAN preprocessors

The quality of code generated by two commercially available FORTRAN preprocessors is examined. These preprocessors augment FORTRAN with ‘structured’ control structures such as the IF-THEN-ELSE and WHILE statements. Two versions of benchmark programs were written and tested, one version produced by the preprocessor, the other, performing the same computation, produced by careful hand-coding directly in FORTRAN. The code generated by the preprocessor and the code written directly in FORTRAN were then compiled. The resulting object modules were then compared for relative execution time and size. This experiment was repeated on three computers, and five compilers with various optimization levels. The results indicate that a substantial overhead in storage space may be paid by using a preprocessor rather than direct coding in FORTRAN, and that in some cases execution time may be increased somewhat by using a FORTRAN preprocessor.     

A framework for preprocessor‐aware C source code analyses

Analyses of C source code usually ignore the C preprocessor because of its complexity. Instead, these analyses either define their own approximate parser or scanner, or else they require that their input already be preprocessed. Neither approach is entirely satisfactory: the first gives up accuracy (or incurs large implementation costs), while the second loses the preprocessor‐based abstractions. We describe a framework that permits analyses to be expressed in terms of both preprocessing and parsing actions, allowing the implementer to focus on the analysis. We discuss an implementation of such a framework that embeds a C preprocessor, a parser, and a Perl interpreter for the action ‘hooks’. Many common software engineering analyses can be written surprisingly easily using our implementation, replacing numerous ad‐hoc tools. The framework's integration of the preprocessor and the parser further enables some analyses that otherwise would be especially difficult to perform. Copyright © 2000 John Wiley & Sons, Ltd.     

一种增强Verilog建模能力的编译预处理器

文章讨论了一种增强Verilog硬件描述语言建模能力的编译预处理器的设计问题。VerilogHDL是专用集成电路设计中应用广泛的一种硬件描述语言,它尚存在一些缺陷。编译预处理器的功能是增强数字系统设计中对模块输入输出端口阵列等参数化设计的能力。在分析IEEEVerilog1364—2001建模特性的基础上,基于LEX和YACC设计出专门的编译预处理器,显著降低了程序规模,可以方便地嵌入其他仿真或综合工具中,增强了VerilogHDL参数化的建模特性。     

Conversion of simulation processes to pascal constructs

Although the expressive power of retentive control is widely accepted, languages possessing such control forms are not always available. In this paper, we present an implementation technique to extend a recursive language to one containing simulation processes. In particular, we report on the design of a preprocessor that translates SimCal, a language that combines Pascal and the process abstraction of Simula, into Pascal. The translation is done automatically by the preprocessor without additional information from the user. The preprocessor has been implemented for a microcomputer using Turbo Pascal, which is also used as the target language. SimCal has been found to be useful for teaching simulation and for programming simulation applications.     

An empirical analysis of c preprocessor use

This is the first empirical study of the use of the C macro preprocessor, Cpp. To determine how the preprocessor is used in practice, this paper analyzes 26 packages comprising 1.4 million lines of publicly available C code. We determine the incidence of C preprocessor usage-whether in macro definitions, macro uses, or dependences upon macros-that is complex, potentially problematic, or inexpressible in terms of other C or C++ language features. We taxonomize these various aspects of preprocessor use and particularly note data that are material to the development of tools for C or C++, including translating from C to C++ to reduce preprocessor usage. Our results show that, while most Cpp usage follows fairly simple patterns, an effective program analysis tool must address the preprocessor. The intimate connection between the C programming language and Cpp, and Cpp's unstructured transformations of token streams often hinder both programmer understanding of C programs and tools built to engineer C programs, such as compilers, debuggers, call graph extractors, and translators. Most tools make no attempt to analyze macro usage, but simply preprocess their input, which results in a number of negative consequences; an analysis that takes Cpp into account is preferable, but building such tools requires an understanding of actual usage. Differences between the semantics of Cpp and those of C can lead to subtle bugs stemming from the use of the preprocessor, but there are no previous reports of the prevalence of such errors. Use of C++ can reduce some preprocessor usage, but such usage has not been previously measured. Our data and analyses shed light on these issues and others related to practical understanding or manipulation of real C programs. The results are of interest to language designers, tool writers, programmers, and software engineers.     

基于TS201的SAR方位向预处理器的优化设计

为满足高分辨率、多模式合成孔径雷达(SAR)系统的方位向预处理需要,利用AD公司的高速DSP芯片ADSP-TS201来实现预处理功能,提高了距离向处理点数、FIR滤波器阶数和运算精度。预处理参数可以根据不同的需要实时改变。该文介绍了预处理器的原理,针对TS201的内部结构和指令特点对软件代码进行优化。实测表明,该预处理器在采用64阶FIR预滤波器、降4倍采样、输入距离线为16 384点时,PRF超过1 800 Hz。     

Snort平台下基于BP网络的预处理插件

在Snort平台使用预处理插件的基础上,提出使用BP神经网络实现一个入侵检测预处理插件.该插件使用改进的BP算法,分为训练部分和检测部分.训练部分是独立的系统,使用样本数据训练得出网络结构参数;检测部分作为插件使用得到的参数构造BP网络并集成到snort中.给出了插件训练部分的详细实现方式,实验结果表明,该插件对异常网络数据包具有较高的检测率,是一种有效的入侵检测系统插件.     

A shorthand preprocessor for IDMS COBOL

Aspects of software development using Codasyl COBOL DML are considered. In limited trials, a preprocessor which makes a terse DML syntax available has been found to increase programmer productivity and improve software quality.     

C语言中编译预处理命令的解读与应用

编译预处理是由预处理程序模块负责完成,在编译前对源程序进行的预加工处理,是C语言的一个重要特点。对C语言中编译预处理的3条命令define、include、ifdef进行了详细分析,用实例对其特殊功能和用法做了详细的阐述,对C语言编译预处理命令的分析对C语言教学和学习都有帮助作用。     

基于FPGA的SAR预处理器中FIR滤波器的实现

针对合成孔径雷达(SAR)预处理器的技术要求,提出了一种采用现场可编程门阵列器件FPGA并利用窗函数法实现线性FIR数字滤波器硬件电路的设计方案,并以一个16阶低通FIR数字滤波器电路的实现为例说明了利用Xilinx公司的Virtex-E系列芯片的设计过程。对于耗时且占资源的乘累加运算,我们给出了将乘累加运算转化为查表的分布式算法(DA算法)。设计的电路通过软件程序进行了验证和硬件仿真,结果表明电路工作正确可靠,能满足设计要求。     

基于FPGA的空域精细可扩展编码预处理器

FPGA越来越多地应用于各种数字信号处理系统中。针对空域精细可扩展编码算法，提出一种基于FPGA的预处理器设计方案，该编码预处理器占用较少的外部存储空间缓存帧数据，充分利用数据操作之间的并行性和流水性，生成视频数据的多描述码流。FPGA实现结果表明，该预处理器能满足应用空域精细可扩展编码算法的视频压缩传输系统的功能要求和实时性要求。     

空域精细可扩展编码预处理器的设计和实现

为了更好地运用空域精细可扩展编码算法，提出了一种编码预处理器的设计方案。该方案占用较少的外部存储空间缓存帧数据，充分利用数据操作之间的并行性和流水性，生成视频数据的多描述码流。仿真结果表明，该方案能满足空域精细可扩展编码算法的功能和实时性要求。     

表面肌电信号前端处理系统

设计了高共模抑制比的表面肌电信号前端处理系统。采用并联型双运放差动放大器、阻容耦合电路以及仪器放大器INA128构成初级放大电路对微弱的表面肌电信号进行放大,并获得高输入阻抗和高共模抑制比;引入屏蔽驱动、右腿驱动以及浮地电源来进一步提高系统的共模抑制比和抗干扰能力;设计高通和低通滤波器以及50 Hz工频陷波器,对不同频段的噪声进行滤除。通过实验测试,该系统具有较强的抗干扰能力,并且能够有效滤除噪声、抑制工频干扰,满足表面肌电信号去噪和放大的要求。     

Andorra-I compilation

Andorra-I is an experimental parallel Prolog system which transparently exploits both dependent and-parallelism and or-parallelism. One of the main components of Andorra-I is its preprocessor. In order to obtain efficient execution of programs in Andorra-I, the preprocessor includes a compiler for Andorra-I. The compiler includes a determinacy analyser and a clause compiler, and generates code for a specialised abstract machine. In this paper we discuss the main issues in the Andorra-I compiler, presenting its abstract instruction set and describing the algorithms used in its implementation.     

Fast image classification using a sequence of visual fixations

Based on human retinal sampling distributions and eye movements, a sequential resolution image preprocessor is developed. Combined with a nearest neighbor classifier, this preprocessor provides an efficient image classification method, the sequential resolution nearest neighbor (SRNN) classifier. The human eye has a typical fixation sequence that exploits the nonuniform sampling distribution of its retina. If the retinal resolution is not sufficient to identify an object, the eye moves in such a way that the projection of the object falls onto a retinal region with a higher sampling density. Similarly, the SRNN classifier uses a sequence of increasing resolutions until a final class decision is made. Experimental results on texture segmentation show that the preprocessor used in the SRNN classifier is considerably faster than traditional multiresolution algorithms which use all the available resolution levels to analyze the input data.     

基于VHDL高级综合的条码阅读预处理器的FPGA设计

文中定义了条码阅读处理器的功能，给出其ＶＨＤＬ语言的行为源描述，讨论了在ＶＨＤＬ高级综合系统ＨＬＳ／ＢＩＴ的支持下面向ＦＰＧＡ，从算法级行为描述开始，自顶向下地进行条码阅读预处理器的设计过程，从中可见，ＶＨＤＬ高级综合和ＦＰＧＡ的结合，是一种简化设计复杂度，提高设计时效的ＡＳＩＣ的简便方法。     

实时Java平台的类预处理器研究

设计并实现一种针对32 bit嵌入式实时Java平台的类预处理器,通过把标准class文件转换成适合Java处理器——Jpor32直接执行的内存映像,将在运行时动态装载和解析class的工作交由类预处理器提前完成,从而消除影响运行时实时性的一些操作,并降低Java处理器的设计复杂性。     

A review of ridge counting in dermatoglyphics

This paper reviews the problem of counting ridges in a digitized fingerprint and examines an interactive software system that relieves the tedium of visual inspection and standardizes the counting procedure. The software system includes digitizer, preprocessor and counter subsystems. The preprocessor smoothes and thresholds the image. The counter defines an appropriate window around the line between two user-selected points, eliminates artifacts and counts runs of zero pixels. A preliminary experiment with a counter based on the Hough transform is also briefly discussed.     

预处理插件在IPv6入侵检测系统中的应用

Snort是一个功能强大的轻量级NIDS,它能够检测出各种不同的攻击方式,并能对攻击进行实时告警.针对Snort没有提供对IPv6地址前缀攻击检测支持的问题,提出利用预处理插件检测该类攻击的解决方案,给出了插件的检测流程.实验结果表明,该插件对地址前缀欺骗攻击具有较高的检测率,是一种有效的入侵检测系统插件.